Speculation: Ryzen 4000 series/Zen 3

[Veradun]

PC sales are actually down around 12% for the first quarter of 2020.

YoY or QoQ?

 

[arandomguy]

Shipments are down YoY.

Most (all?) of those industry research firms track shipments and not end user sales. So it's typically not clear exactly how much is due to supply side issues (China lockdown due to the virus being a factor currently) versus demand dropping leading to order cut backs.

 

[Markfw]

It took Intel 6-12 months to create a desktop part for the 10th gen (still not out) after their mobile variant. I am worried that AMD will do the same. When I see estimates of when is Zen 3 coming, I think it may be that plus another 6 months till the desktop chips come out.

Perhaps Intel is just so focused on the mobile market because they have an advantage over AMD where on the desktop, they don't.

Renoir just came out. AMD now has an advantage over Intel in mobile now as well. So now AMD OWNS desktop, mobile, HEDT and servers.

 

[lobz]

I'm skeptical of the idea that everyone isn't cutting orders due to the virus.

The virus should even increase demand for tech.

 

[Muadib]

YoY or QoQ?

PC sales suffer worst decline since 2013 due to coronavirus outbreak

Gartner estimates that 51.6 million PC units were shipped in the first quarter, down 12.3% from the previous year.

www.cnbc.com

 

[Ajay]

Renoir just came out. AMD now has an advantage over Intel in mobile now as well. So now AMD OWNS desktop, mobile, HEDT and servers.

They don't own anything yet. They have an advantage in technical specs. It's along way from there to marketing success. Just think about how much money Intel has pumped into supporting it partners over the years with joint marketing dollars. How much money Intel has spent on direct marketing dollars to consumers and businesses alike. Having a great processor isn't going to change that overnight (or even close to that). I admire your enthusiasm, but AMD has a long hard slog ahead of them.

 

[Markfw]

They don't own anything yet. They have an advantage in technical specs. It's along way from there to marketing success. Just think about how much money Intel has pumped into supporting it partners over the years with joint marketing dollars. How much money Intel has spent on direct marketing dollars to consumers and businesses alike. Having a great processor isn't going to change that overnight (or even close to that). I admire your enthusiasm, but AMD has a long hard slog ahead of them.

Well, actually you have a very good point. I made the part red to say what I really meant. I also mean in real performance, not just the spec. But as you pointed out SALES is the ultimate thing that makes them OWN the markets.

 

[eek2121]

PC sales are actually down around 12% for the first quarter of 2020.

Not anymore! I am willing to bet we won’t see much change in demand, we may possibly see higher growth due to remote work requirements.

 

[Markfw]

Not anymore! I am willing to bet we won’t see much change in demand, we may possibly see higher growth due to remote work requirements.

Both my son and his wife have been forced by law to work from home (Washington State) That or no pay. I donated a computer and a monitor (only a 10 core for drafting)

The kids are driving them crazy. Especially my very active 3 year old grandson !

 

[lobz]

It is correct how it is written, at least from what I’ve seen.

mobile Intel > AMD mobile
Desktop AMD > Intel desktop (CPU)

You, sir, have just won the funniest comment of the month award.

 

[darkswordsman17]

It took Intel 6-12 months to create a desktop part for the 10th gen (still not out) after their mobile variant. I am worried that AMD will do the same. When I see estimates of when is Zen 3 coming, I think it may be that plus another 6 months till the desktop chips come out.

Perhaps Intel is just so focused on the mobile market because they have an advantage over AMD where on the desktop, they don't.

You do know that mobile chips are basically the last chips that AMD brings out with each gen of Zen? They might be the first to get the next numerical designation, but they're based on the previous gen chips (the 4000 series laptop chips are Zen 2, the 4000 series chips elsewhere will be Zen 3). Well the desktop APUs lag behind those but are based on the same chips. The desktop CPUs are just about the first chips launched with each gen of Zen. You can argue EPYC is, but I think that's just sampling to their best partners (I think official launch of EPYC happens after desktop Zen chips, but before Threadripper). I think they announce them (and start sampling first).

Which things might change but I doubt they do this year. I think it'd take a pretty big situation to keep Zen 3 from launching this year.

 

[amrnuke]

It is correct how it is written, at least from what I’ve seen.

mobile Intel > AMD mobile
Desktop AMD > Intel desktop (CPU)

Technically, it's the opposite:
AMD mobile > Intel mobile
AMD desktop ~~ Intel desktop (single core Intel > single core AMD, multi core AMD > single core AMD)
AMD server > Intel server

In real life, Intel mobile and desktop and server >>>> AMD because they keep dumping money to compensate for their technical disadvantage.

 

[Thunder 57]

Technically, it's the opposite:
AMD mobile > Intel mobile
AMD desktop ~~ Intel desktop (single core Intel > single core AMD, multi core AMD > single core AMD)
AMD server > Intel server

In real life, Intel mobile and desktop and server >>>> AMD because they keep dumping money to compensate for their technical disadvantage.

Depends on the task. Most applications favor AMD, while most games do better on Intel. So it may be fair to say they are about equal, but saying Intel single core is better than AMD single core isn't exactly fair. AMD also offers more cores for the same price.

 

[uzzi38]

I'm reading through the article again (though granted, only a translation), maybe I'm just reading it wrong, but doesn't it read like the 20k wpm for AMD is referring to N5? Someone tell me I'm going crazy, right? If I were to sumarrize the chain of events:

- Huawei cut fourth quarter (2020 or 2021?) wafer orders for N5 due to low smartphone demand
- TSMC didn't have an issue with buyers however, as Apple ate up that wafer supply, competing with AMD for it.
- AMD's capacity requirement for the node is no less than 12k wpm

Somebody please tell me I'm crazy for thinking what I'm thinking.

 

[DisEnchantment]

Well, actually you have a very good point. I made the part red to say what I really meant. I also mean in real performance, not just the spec. But as you pointed out SALES is the ultimate thing that makes them OWN the markets.

Even after AMD "OWN" the market, surprises are springing left and right for pro users, luckily for them they usually know what the problem is, instead of thinking what is wrong with the processor which is beating the Core i9 in benchmarks, but dog slow in their applications.

Years of "contribution" from Intel has ensured that that most open source code is no longer vendor agnostic. For closed source applications you can bet MDF and arm twisting can really cripple performance.
And even when you contribute, ... lo and behold, Intel engineers are the (co)maintainers
Years of wrangling with the maintainers and one fine day they approve your PR but guess what ... They have come up with a comparable implementation in the mean time.

 

[DisEnchantment]

I'm reading through the article again (though granted, only a translation), maybe I'm just reading it wrong, but doesn't it read like the 20k wpm for AMD is referring to N5? Someone tell me I'm going crazy, right? If I were to sumarrize the chain of events:

- Huawei cut fourth quarter (2020 or 2021?) wafer orders for N5 due to low smartphone demand
- TSMC didn't have an issue with buyers however, as Apple ate up that wafer supply, competing with AMD for it.
- AMD's capacity requirement for the node is no less than 12k wpm

Somebody please tell me I'm crazy for thinking what I'm thinking.

I read the same thing, I asked @kokhua what is it for but there is no clarity.
30K wpm N7(+/P) from Q2 and then 12K wpm N5 from Q4.

I am wondering if the report is correct or it could be they mis quoted someone. For example it could be that AMD got extra wpm but does not mean N5 because the processes share a lot of common equipment and capacity taken out from N5 could be used for N7 for example.

However, if true ...

 

[uzzi38]

I read the same thing, I asked @kokhua what is it for but there is no clarity.
30K wpm N7(+/P) from Q2 and then 12K wpm N5 from Q4.

I am wondering if the report is correct or it could be they mis quoted someone. For example it could be that AMD got extra wpm but does not mean N5 because the processes share a lot of common equipment and capacity taken out from N5 could be used for N7 for example.

However, if true ...

Yeah precisely. And I've been wondering something since the FAD now as well at the same time:

How come we got roadmaps for desktop and servers... but none for APUs?

Maybe it's just me. I could be going completely loco and have no clue what I'm talking about. But there's a lot of REALLY weird coincidences right now. First Van Gogh rumours, after that FAD takes place and no mention of 25x20 nor any APU roadmaps, now after that this pops up?

I seriously feel like I'm overthinking things way too hard.

 

[DisEnchantment]

Looks like Zen3 is having bump in the size of the microcode needed.

This should indicate a change for the core architecture decode/execute/dispatch subsystem.

x86/microcode/AMD: Increase microcode PATCH_MAX_SIZE - kernel/git/tip/tip.git - Unnamed repository; edit this file 'description' to name the repository.

git.kernel.org

Uncore/L3 are also has major changes indicated below with a new LS architecture that we already knew.

https://github.com/torvalds/linux/commit/89a76171bf50bd20d44338408b8c09433c302956

Sounds like a big overhaul.

There was an AMD patent for virtualization of the MicroOp cache. I wonder if it is related .

20200019406 : METHOD AND APPARATUS FOR VIRTUALIZING THE MICRO-OP CACHE

Spoiler

Abstract
Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

 

[DrMrLordX]

Looks like Zen3 is having bump in the size of the microcode needed.

Just for clarification, is that going to have any effect on UEFI file sizes?

 

[DisEnchantment]

Just for clarification, is that going to have any effect on UEFI file sizes?

Not so much, just the microcode is quite tiny in the overall picture. several Kilobytes.
e.g. the 1.0.0.5 Matisse Microcode is 4 KB raw.
However different CPUs can have different microcode so they add up.
Then there are the other things related to PSP, CBS and such which makes the BIOS bigger.
The microcode itself only comprise of all things (like how instructions are handled) that the HW does not have already or if the behaviour is changed.

 

[Olikan]

Looks like Zen3 is having bump in the size of the microcode needed.

This should indicate a change for the core architecture decode/execute/dispatch subsystem.

x86/microcode/AMD: Increase microcode PATCH_MAX_SIZE - kernel/git/tip/tip.git - Unnamed repository; edit this file 'description' to name the repository.

git.kernel.org

Uncore/L3 are also has major changes indicated below with a new LS architecture that we already knew.

https://github.com/torvalds/linux/commit/89a76171bf50bd20d44338408b8c09433c302956

Sounds like a big overhaul.

There was an AMD patent for virtualization of the MicroOp cache. I wonder if it is related .

20200019406 : METHOD AND APPARATUS FOR VIRTUALIZING THE MICRO-OP CACHE

Spoiler

Abstract
Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

Hold on, this isn't virtual pages right? (I mean, it is a known x86 bottleneck, would be neat if AMD fixed that)

 

[DisEnchantment]

Hold on, this isn't virtual pages right? (I mean, it is a known x86 bottleneck, would be neat if AMD fixed that)

I am not aware of this limitation but I don't think it is that. Do you have a link?

AMD did make some work with paging indeed but to support encryption with SEV.
In the staging repos for the linux kernel there is a barrage of commits related to Paging and SEV-SNP.

 

[Tuna-Fish]

Hold on, this isn't virtual pages right? (I mean, it is a known x86 bottleneck, would be neat if AMD fixed that)

4k page size isn't that much of a bottleneck, and it cannot be fixed in hardware. The reason it has to stay at 4k is that approximately every piece of software ever written for x86 assumes 4k, and can probably fail in imaginative ways if page sizes are increased.

Anyway, good operating systems allow transparent hugepages which remove most of the overhead.

 

[DisEnchantment]

Ah you mean the page size in virtual memory addressing.. This one is unrelated. This is the microcode size not related to virtual memoring paging.

 

[Olikan]

4k page size isn't that much of a bottleneck, and it cannot be fixed in hardware. The reason it has to stay at 4k is that approximately every piece of software ever written for x86 assumes 4k, and can probably fail in imaginative ways if page sizes are increased.

Anyway, good operating systems allow transparent hugepages which remove most of the overhead.

Yes, i am aware of all that... i was wondering if AMD found some kind of extension that is compatible with legacy code