moinmoin
Diamond Member
- Jun 1, 2017
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Not much, but the AT article confirmed that Renoir has two CCXs, meaning the Zen 3 microcode is decisive.
"AMD stated that the Zen 2 design in this chips follows the same CCX layout as the desktop hardware, which means the 8 cores are split into two CCX units which communicate over the internal infinity fabric."
"AMD stated that the Zen 2 design in this chips follows the same CCX layout as the desktop hardware, which means the 8 cores are split into two CCX units which communicate over the internal infinity fabric."
While Renoir will still be based in Zen 2, like the previous APUs it will contain microcode of the next Zen gen, so Zen 3 in this case. If the rumor of Renoir having 8 cores is correct (and it prolly should be, with Intel increasing the number of cores as well), this would mean two CCXs with 4 cores each. The "next gen" microcode would have to handle the increasing latency two CCXs would otherwise introduce while retaining the significantly smaller L3$ size of APUs compared to the server/desktop dies.
To me it sounds like DisEnchantment's interpretation of the patents is spot on (assuming compute block = CCX, so definitely L3$):