Speculation: Ryzen 4000 series/Zen 3

[uzzi38]

Renoir's Zen2/Zen3 won't compete with Tigerlake's Willowcove. Obfuscated rumor: Willowcove will be deploying a something but it is only targeting a single, while Goldencove will deploy the double.

On the GPU side, I have been getting mixed messages. Rumor: TGL-S/TGL-H(8-core WLC Desktop/Mobile) won't be launching with the 32EU igpu, it is actually GT0. It instead will be launching with the small DG1/HBM2e dgpu on package.

Basically, both AMD's 7nm and 5nm APUs will lose out to Intel's ultra-wide power-efficient core/discrete on package projects.

Launch dates:
Renoir -> January 2020 if it isn't delayed like the rumors state.
Tigerlake-U -> June 2020 (quad-core/96 eu)
Tigerlake-H -> August 2020 (octo-core/128 eu) <== There will be a PoC console running a modified clear linux os for gaming.
The desktop -S model being either September or October. (The -H SKU is prioritized)

TigerLake-H is nonexistent. Or perhaps dead is the better term. -H and -S will only come with Alder Lake, if at all.

 

[DisEnchantment]

TSMC's presentation from several months ago on fully 3D stacked ICs. b and d are the new stuffs.

TSMC-SoIC® - Taiwan Semiconductor Manufacturing Company Limited

www.tsmc.com

3D Multi-chip Integration with System on Integrated Chips (SoIC™)

The electrical characterization of System on Integrated Chips (SoIC™), an innovative 3D heterogeneous integration technology manufactured in front-end of line with known-good-die is reported. Chiplets integration of devices including foundry leading edge 7nm FinFET technology with SoIC™...

ieeexplore.ieee.org

System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration

A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency, wilder data bandwidth, higher...

ieeexplore.ieee.org

 

[Adonisds]

How much does each 14nm and 7nm die costs AMD? The 8C bulldozer had a die bigger than 300 mm^2. Do current AMD processors have a much bigger margin, seeing as the dies as much smaller?

 

[uzzi38]

How much does each 14nm and 7nm die costs AMD? The 8C bulldozer had a die bigger than 300 mm^2. Do current AMD processors have a much bigger margin, seeing as the dies as much smaller?

AMD have talked about costs on smaller nodes for the same die size. It's not pretty.

While they have been able to bump up margins, they weren't exactly known for there high margins before. They still fall behind Intel and Nvidia in that regard.

 

[Adonisds]

AMD have talked about costs on smaller nodes for the same die size. It's not pretty.

While they have been able to bump up margins, they weren't exactly known for there high margins before. They still fall behind Intel and Nvidia in that regard.

Is that graph comparing what the costs are now or when each node was introduced? Is 7nm expected to decrease a lot in cost in the next years?

 

[Topweasel]

Not much really specially since they are completely a wafer customer. TSMC is going to set a price on their wafer supply on each node. They are going to make their money on keeping a base maybe razor thin margin sale early in the process vs. after their equipment and r&d has been paid for to continue to offer the wafers at that price.

 

[moinmoin]

How much does each 14nm and 7nm die costs AMD? The 8C bulldozer had a die bigger than 300 mm^2. Do current AMD processors have a much bigger margin, seeing as the dies as much smaller?

The bigger problem nowadays is not the wafer cost (which does increase as well) but the upfront cost for design, mask and validation (which has to be recuperated in the actual production first):

AMD did increase their margin, both by using as few distinct dies as possible (like Zeppelin for Zen), as well as decreasing the die size by going with a chiplets architecture for Zen 2 (here's a size comparison of AMD's chips since 1997).

 

[Adonisds]

Is trying to make the costumer pay more the only reason Intel and AMD sell processors without SMT/HT? Are there chips that could be usable with SMT off that couldn't with SMT on?

 

[Veradun]

Is trying to make the costumer pay more the only reason Intel and AMD sell processors without SMT/HT? Are there chips that could be usable with SMT off that couldn't with SMT on?

It's called market segmentation, would you rather only have 3950X and 9900KS as a buyable option?

On the second question the answer is yes but no :>

 

[amd6502]

Is trying to make the costumer pay more the only reason Intel and AMD sell processors without SMT/HT? Are there chips that could be usable with SMT off that couldn't with SMT on?

Yes much of it is market segmentation. There are often some physical reasons though, at least on the AMD side. It's a way to make lower binning make the TDP cutoff or behave better thermally; this is relevant because low binning is usually 'overvolted.' Secondly it compensates for lower frequencies by boosting thread IPC under a wide range of use by ensuring that shared resources are minimized. Thus a thread will always get the full L2, the full core, and more L3.

 

[DisEnchantment]

SNP will most likely make it to Zen 3 as well.

https://static.sched.com/hosted_files/lsseu2019/65/SEV-SNP%20Slides%20Nov%201%202019.pdf

 

[moinmoin]

SNP will most likely make it to Zen 3 as well.

View attachment 13293

https://static.sched.com/hosted_files/lsseu2019/65/SEV-SNP%20Slides%20Nov%201%202019.pdf

A video of the talk from which that is the slides:

An earlier talk giving a more general overview over SEV:

 

[DisEnchantment]

When asked about what kind of performance gain Milan's CPU core microarchitecture, which is known as Zen 3, will deliver relative to the Zen 2 microarchitecture that Rome relies on in terms of instructions processed per CPU clock cycle (IPC), Norrod observed that -- unlike Zen 2, which was more of an evolution of the Zen microarchitecture that powers first-gen Epyc CPUs -- Zen 3 will be based on a completely new architecture.


Norrod did qualify his remarks by pointing out that Zen 2 delivered a bigger IPC gain than what's normal for an evolutionary upgrade -- AMD has said it's about 15% on average -- since it implemented some ideas that AMD originally had for Zen but had to leave on the cutting board. However, he also asserted that Zen 3 will deliver performance gains "right in line with what you would expect from an entirely new architecture."

Taken from here

AMD Inks New Server CPU Deals; Data Center Chief Discusses Them and More

During a talk with TheStreet, AMD exec Forrest Norrod highlighted new supercomputer deals and an expanded partnership with AWS. He also suggested AMD's next-gen server CPUs will deliver healthy performance gains.

realmoney.thestreet.com

What is Forrest hinting, an entirely new arch in Zen3? Was not expecting this, very interesting.

https://twitter.com/x/status/1196435240597757955

 

[Topweasel]

They have been clear in stating the Zen 2 and 3 and so on were distinct architectures rather then some tweaks here or there or a process change. Not all of that means major changes to the core design. Zen 2 didn't change much about how the core worked compared to Zen 1 but the rest of the architecture had massive changes to how the dies connected to each other and the rest of the system. Zen 3 isn't going to be built from the ground up, it will probably look like Zen for the most part. But I look at it this way.

Zen 1 was about creating a competitive die and connecting them.
Zen 2 was about taking the dies and perfecting the connection for balanced and quick performance.
Zen 3 will probably about designing the core arch around the idea of using the now perfected connection. Probably room for improvement if the cores, ccx's (if they are needed) and CDD's are designed with IO die and IF multi-die connectivity from the beginning.

 

[soresu]

Taken from here

AMD Inks New Server CPU Deals; Data Center Chief Discusses Them and More

During a talk with TheStreet, AMD exec Forrest Norrod highlighted new supercomputer deals and an expanded partnership with AWS. He also suggested AMD's next-gen server CPUs will deliver healthy performance gains.

realmoney.thestreet.com

What is Forrest hinting, an entirely new arch in Zen3? Was not expecting this, very interesting.

The forthcoming SEV-SNP extension sounds like a significant addition at the very least, though I have little idea just what would need to be changed to support it.

Either way it's good to see AMD continue to push security, especially when Intel is taking so many hits over their own deficiencies.

The mentioned "purpose built" GPU for Radeon Instinct sounds like Arcturus, which I believe to be a raster stripped dual Vega 20 MCM esque package (by which I mean similar to dual Vega 20 GPU's on one package, likely 8 HBM stacks, 4 per GPU die).

 

[exquisitechar]

What is Forrest hinting, an entirely new arch in Zen3? Was not expecting this, very interesting.

"Entirely new arch" can mean many things, probably not the term I'd use for Zen 3. But it doesn't matter, what matters is that he is strongly hinting at a large IPC increase, just like I had predicted based on rumors and some things that we know. Higher clocks for Milan are confirmed, too.

 

[Ajay]

Zen 1 was about creating a competitive die and connecting them.
Zen 2 was about taking the dies and perfecting the connection for balanced and quick performance.
Zen 3 will probably about designing the core arch around the idea of using the now perfected connection. Probably room for improvement if the cores, ccx's (if they are needed) and CDD's are designed with IO die and IF multi-die connectivity from the beginning.

I think one of the major architectural changes is the elimination of CCXs. Everything will be a CCD from Zen3 onward. Norrod didn’t specify‘micro architecture' changes. This could just be a matter of semantics given the target audience. Whatever changes we will see, it appears that Zen3 won’t be bringing the same level of performance increase as we saw with Zen2 (too bad, but realistic).

 

[Ajay]

"Entirely new arch" can mean many things, probably not the term I'd use for Zen 3. But it doesn't matter, what matters is that he is strongly hinting at a large IPC increase, just like I had predicted based on rumors and some things that we know. Higher clocks for Milan are confirmed, too.

Unless my reading glasses have suddenly malfunctioned, IPC changes will not be as large as Zen2 produced. Also, I didn’t see where anything was said about large clock increases. The 7nm+ process just doesn’t offer that much frequency headroom.

 

[uzzi38]

I think one of the major architectural changes is the elimination of CCXs. Everything will be a CCD from Zen3 onward. Norrod didn’t specify‘micro architecture' changes. This could just be a matter of semantics given the target audience. Whatever changes we will see, it appears that Zen3 won’t be bringing the same level of performance increase as we saw with Zen2 (too bad, but realistic).

Forrest Norrod is the server guy from AMD there to talk about server chips. 8 core CCXes is not a change that would drastically improve performance on servers. For clients it most definitely is, but for servers? A nice to have, but by no means essential nor a large performance bump. There will be much more than that.

Not getting the same kind of performance bump as Zen 2 isn't surprising in the slightest. I mean, who here was actually expecting the kind of performance bump you get from doubling core count, increasing clocks AND an extra 15% IPC on top?

No, Milan will still be a 'generational' increase. 'It's no 2+x performance increase, but should not be treated as a marginal improvement' is the takeaway you should have from this.

 

[exquisitechar]

Unless my reading glasses have suddenly malfunctioned, IPC changes will not be as large as Zen2 produced.

On what do you base this? Norrod literally says that Zen 2 was an evolution while Zen 3 is a "completely new microarchitecture" and also that it will deliver performance gains "right in line with what you would expect from an entirely new architecture." Also how AMD is adopting a "tick-tock" model and that Zen 2 is a tick while Zen 3 is a tock.

As a whole, Zen 2 obviously will not be matched in its performance increase, as it leveraged 7nm to double core counts and increase the clock speeds. IPC alone, however? I bet that Zen 3 will match the Zen -> Zen 2 increase or exceed it slightly.

Also, I didn’t see where anything was said about large clock increases. The 7nm+ process just doesn’t offer that much frequency headroom.

Not large. The clock speed increase will be marginal in most cases, probably especially for the high end Ryzen CPUs.

 

[HurleyBird]

Forrest Norrod is the server guy from AMD there to talk about server chips. 8 core CCXes is not a change that would drastically improve performance on servers. For clients it most definitely is, but for servers? A nice to have, but by no means essential nor a large performance bump. There will be much more than that.

Improving core-to-core latency would help with desktop more, but that might actually see a regression inside the CCX. The fact that the amount of L3 is effectively doubled is probably a greater benefit in the server space.

 

[Ajay]

On what do you base this? Norrod literally says that Zen 2 was an evolution while Zen 3 is a "completely new microarchitecture" and also that it will deliver performance gains "right in line with what you would expect from an entirely new architecture." Also how AMD is adopting a "tick-tock" model and that Zen 2 is a tick while Zen 3 is a tock.

As a whole, Zen 2 obviously will not be matched in its performance increase, as it leveraged 7nm to double core counts and increase the clock speeds. IPC alone, however? I bet that Zen 3 will match the Zen -> Zen 2 increase or exceed it slightly.

No, he's essentially pointing out that the Zen1->Zen2 increase will not happen.

Norrod did qualify his remarks by pointing out that Zen 2 delivered a bigger IPC gain than what's normal for an evolutionary upgrade -- AMD has said it's about 15% on average -- since it implemented some ideas that AMD originally had for Zen but had to leave on the cutting board. However, he also asserted that Zen 3 will deliver performance gains "right in line with what you would expect from an entirely new architecture."

Zen1 left some low hanging fruit on the table, which was implemented in Zen2; giving Zen2 a bigger than average boost. I'm not pissing on Zen3, restating the reasonable expectations set out by Norrod.

 

[Hitman928]

Zen1 left some low hanging fruit on the table, which was implemented in Zen2; giving Zen2 a bigger than average boost. I'm not pissing on Zen3, restating the reasonable expectations set out by Norrod.

I think you need to put it in context with regards to his comments on Zen 3.

Norrod observed that -- unlike Zen 2, which was more of an evolution of the Zen microarchitecture that powers first-gen Epyc CPUs -- Zen 3 will be based on a completely new architecture. Norrod did qualify his remarks by pointing out that Zen 2 delivered a bigger IPC gain than what's normal for an evolutionary upgrade -- AMD has said it's about 15% on average -- since it implemented some ideas that AMD originally had for Zen but had to leave on the cutting board. However, he also asserted that Zen 3 will deliver performance gains "right in line with what you would expect from an entirely new architecture."

Reads to me like Zen 2 had higher IPC gains than expected as an evolutionary step (tick) but that AMD expects to be able to reach that much or more when stepping up to a new architecture (tock) as that is where the planned IPC gains are to begin with. Maybe it's just PR speak, but to me Mr. Norrod sets the expectation to see at least another Zen to Zen 2 type IPC increase with Zen 3, maybe more.

 

[dnavas]

No, he's essentially pointing out that the Zen1->Zen2 increase will not happen.

I'm not currently capable of reading the quotes as written as supporting your point of view.

However, he also asserted that Zen 3 will deliver performance gains "right in line with what you would expect from an entirely new architecture."

Zen1->Zen2 IPC increase was larger than typical of an evolutionary upgrade. Zen2->Zen3 is typical of an entirely new architecture. The only way I see to support your line of thinking here is to claim that the Zen2 IPC increase was not just larger than the typical evolutionary upgrade, but also larger than an upgrade in architecture. That is not what was said. It may be true, mind you, but that isn't what is claimed in the article.

 

[Ajay]

Zen1->Zen2 IPC increase was larger than typical of an evolutionary upgrade. Zen2->Zen3 is typical of an entirely new architecture. The only way I see to support your line of thinking here is to claim that the Zen2 IPC increase was not just larger than the typical evolutionary upgrade, but also larger than an upgrade in architecture. That is not what was said. It may be true, mind you, but that isn't what is claimed in the article

Fine, whatever. We are just going around in circles based on a couple of lines of text that can apparently be interpreted several ways. As usual, we'll have to wait and see. Maybe AMD is sandbagging Zen3 performance a bit; I suppose we can hope that that is the case.