However instead of doubling L3 cache, which brings few % performance and wasting a lot transistors, they can use it more efficiently.
They need that big L3 to hide latencies between the CCD and IOD.
The transition from N7 to N7+ won't bring much in terms of clock speed (I would suppose 150 to 250 MHz tops if at all), so AMD has to improve in other areas to bump up performance.
Since it is going to be a major architecture update, unlike Ryzen 2K aka Zen+, we should expect some decent generational gains similar to the transition from Zen+ to Zen2.
Same thoughts to ponder like before,
- How will they spend the transistor budget. The small density increase afforded by the N7+ could come in handy to improve the core itself.
- What about the Cores? Will there be a more Int/FP units? Also front end improvements?
- Will there be some memory stacked on the dies this time? It has been so conistently depicted in most of AMD's patents.
- There are patents to make the L3 Directory visible across all CCXs, would this make it to Zen 3?
- How will they solve the temperature hotspots, will the Thermo electric cooler patent make it to the product? Although this is for 3D stacked chiplets
- How will the IO chiplet evolve, still on 12nm? A reduction in size of the IOD could afford some more wiggling space for bigger core improvements.
- Will the dies be glued together using an interposer this time, as described in most of the patents.
- How will the dies be packaged? Full 3D will come in Zen4 I believe. What would a 2.5D packaging look like?
- IOD to CCD latency, IF improvements? I would suppose they will need to concentrate on this instead of only relying on that massive L3 to hide the latency. Inter Core latency is already quite low on Zen2.
Interestingly, TSMC announced N7P. I wonder if this could go in some of the later Ryzen 3k SKUs? Or is this already what is being used in the Ryzen 3k?
N7+ will be a long node for AMD, all the consoles will also be on it.