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Speculation: Ryzen 4000 series/Zen 3

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Mar 11, 2004
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You're repeating a common opinion that if Apple (or anyone really) wanted to, they could scale up an ARM design and it would destroy everything. It's not that simple. Others can surely explain it better than I, but you can't just say that because it runs at x GHz and q voltage, it can run at y GHz at p voltage. So many different things affect frequency.

If there were massive gains to be had, someone would be doing it. Software is a problem, but less so every day. Apple surely has the money, but not all of the necessary technology. To answer your question, Zen+ at it's lowest p-state of 2.2GHz only needs about 0.75v on my 2600X. I think it's actually 0.775v but it bounces around so much because of background tasks it never stays there long.

I wish I could give you a better answer about high performance ARM and hopefully someone else can. You may find this article to be informative, though.
I think Apple would develop a separate core (entirely separate SoC really) for such a move, so I don't think it'd be simply them pushing the clock speeds up. They like to take things slow though, and they've been working on kinda merging/porting some of their software (not unlike what they started doing leading up to them moving from Power to Intel/x86). I think it'd be a relatively slow transition though, where Apple will start by shifting the SoC that goes in the iPad Pros into the Macbook Air and Macbook (non Pros). The iPhone and regular iPads would share a SoC. Then probably a few years later we see them move the Macbook Pros and iMac to a third SoC.

Let's not forget the GloFo issues. AMD wisely didn't commit to them by the looks they were able to switch to TSMC. That could have bit them hard but I think it only cost them 1-2 months. Who really knows, though? I expect to see Zen 3 in late August at best to mid October at worst.
AMD shouldn't have similar delay, and I'd guess they won't have as much issues related to I/O stuff. I don't see why Zen 3 shouldn't be ready for Computex. As far as I know, TSMC's 7+ is on track, and already volume production - think Apple's SoC that is in the new iPhones is using it).

I could see AMD stretching things out more. Zen 2 Threadripper at CES (where it becomes the top gaming CPU by having largest L3 cache, highest clock speeds, and most power/thermal room). Where it launches shortly after. Probably Zen 2 APUs (monolithic ones for laptops for instance, not sure on chiplet ones, if we get those they probably won't show up til Computex, but we might see them do something like skip right to Zen 3 CPU chiplet). Possibly Navi 20 announcement with it launching in the spring (or maybe around E3). E3 we get new console announcements. Computex we get Zen 3 Ryzen and then Zen 3 EPYC launches fully end of summer (same time as now). Then the fall we get new console launches. Not sure on Arcturus, its supposed to be out next year, but not sure in what respect. But if Navi 20 were to be out early, they could have Arcturus out for a fall launch. I'm not sure if there'd be any concern about upstaging the consoles, so I could see them possibly waiting for CES 2021 to announce Arcturus. They could possibly put it into production end of 2020 and have it ready for launch. It could also be part of them changing to a new product stack setup (i.e. splitting consumer and pro GPUs), where Arcturus would be a top down consumer launch (and feature probably GDDR6). Or maybe the pro stuff just goes to chiplets with an I/O die on an interposer with HBM).
 

Saylick

Senior member
Sep 10, 2012
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There was 1.5 year between "design complete" and release of zen2.
Design Zen3 is complete now, so Zen3 in Q1 2021 ?
(Based on intels speed/delays they could actually do that)

Although Zen3 comes probably sooner like end 2020, Zen2 was a big change on all design levels.
Agreed, I'm thinking Zen 3 comes out Q3 2020. Zen 2 involved transitioning to a new node along with moving to a chiplet-based design while Zen 3 will build upon Zen 2 more so than establish a new design paradigm, so AMD should be able to bring it to market quicker than it took them to bring out Zen 2.
 

scannall

Golden Member
Jan 1, 2012
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Agreed, I'm thinking Zen 3 comes out Q3 2020. Zen 2 involved transitioning to a new node along with moving to a chiplet-based design while Zen 3 will build upon Zen 2 more so than establish a new design paradigm, so AMD should be able to bring it to market quicker than it took them to bring out Zen 2.
At some point they will finally be free of the WSA with Global Foundries. Maybe Zen 4? The I/O die on 7nm or 5 nm will be a nice step forward as well.
 

Thala

Golden Member
Nov 12, 2014
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You're repeating a common opinion that if Apple (or anyone really) wanted to, they could scale up an ARM design and it would destroy everything. It's not that simple. Others can surely explain it better than I, but you can't just say that because it runs at x GHz and q voltage, it can run at y GHz at p voltage. So many different things affect frequency.
First of all i am not expressing my opinion but just physics. The fact that higher voltages leading to higher currents leading to higher frequencies is affecting every digital circuit in a very similar way within the same process technology. It does not matter if this circuit is from company A or B. If i have a circuit which can be clocked 2.5GHz@0.75V, then it can be clocked around 4GHz+@1.3V - its not too hard to grasp the concept.
 

Thunder 57

Golden Member
Aug 19, 2007
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First of all i am not expressing my opinion but just physics. The fact that higher voltages leading to higher currents leading to higher frequencies is affecting every digital circuit in a very similar way within the same process technology. It does not matter if this circuit is from company A or B. If i have a circuit which can be clocked 2.5GHz@0.75V, then it can be clocked around 4GHz+@1.3V - its not too hard to grasp the concept.
That's nonsense. You are still limited to the frequency of your slowest pipeline stage, for one. Otherwise why couldn't P3 Tualatin clock as high as P4 Northwood?
 
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Thala

Golden Member
Nov 12, 2014
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That's nonsense. You are still limited to the frequency of your slowest pipeline stage, for one.
*sigh* ....
And you slowest pipeline stage also limits your frequency @0.75V - its just that you slowes pipelines stage also gets faster @1.3V - thats the whole point! Hope you start to understand now...

And why does P3 and P4 play a role here? They are not remotely part of my argument. Not sure why you bringing up totally unrelated questions?
 
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Thunder 57

Golden Member
Aug 19, 2007
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*sigh* ....
And you slowest pipeline stage also limits your frequency @0.75V - its just that you slowes pipelines stage also gets faster @1.3V - thats the whole point! Hope you start to understand now...

And why does P3 and P4 play a role here? They are not remotely part of my argument. Not sure why you bringing up totally unrelated questions?
I think you started to reply before my edit. I realized that as soon as I posted it and went to add an example. Shouldn't have posted that quickly. The point is that architecture matters as well. They both came off the same process and ran at similar voltages, but clocked very differently.
 

Thala

Golden Member
Nov 12, 2014
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The point is that architecture matters as well. They both came off the same process and ran at similar voltages, but clocked very differently.
Of course the architecture matters, but thats not my argument at all. My argument is, that if 2 circuits reaching roughly the same frequency at lower voltage, they will also reach roughly the same frequency at higher voltage - because the frequency - voltage curve is similar.

Your P3 vs. P4 question is unrelated because P4 reaches higher frequency at both low and high voltages - so the do not have the same frequency - voltage curve. Why is that - because P4 most likely have shorter critical logic pathes between 2 registers than P3.
 

Thunder 57

Golden Member
Aug 19, 2007
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Of course the architecture matters, but thats not my argument at all. My argument is, that if 2 circuits reaching roughly the same frequency at lower voltage, they will also reach roughly the same frequency at higher voltage - because the frequency - voltage curve is similar.
Fine, then let's compare Tualatin to Thoroughbred. Again similar voltages. P3 topped out at 1.4GHz, Athlon XP hit 1.8GHz. It was revised and hit 2.25GHz. Of course now we are talking about different fabs, but both had excellent 130nm processes at the time.
 
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Thala

Golden Member
Nov 12, 2014
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Fine, then let's compare Tualatin to Thoroughbred. Again similar voltages. P3 topped out at 1.4GHz, Athlon XP hit 2.25GHz. Of course now we are talking about different fabs, but both had excellent 130nm processes at the time.
I am talking about 2 architectures reaching the same frequency at the same voltage at iso process, you are bringing up examples where 2 architectures hit different frequencies at the same voltage.
I never claimed that any 2 architectures can hit the same frequency - only when they hit the same frequency at a reference voltage point.
 

Thunder 57

Golden Member
Aug 19, 2007
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I am talking about 2 architectures reaching the same frequency at the same voltage at iso process, you are bringing up examples where 2 architectures hit different frequencies at the same voltage.
I never claimed that any 2 architectures can hit the same frequency - only when they hit the same frequency at a reference voltage point.
Understood, and you are right, I wasn't making the correct argument. The problem is that trying to find a comparison is like trying to find a unicorn. CPU's are all designed with different characteristics in mind. My next guess would be to go to look at Core 2 Duo vs Athlon 64 X2. Pretty sure there would be a comparison there with comparable voltages but the A64 would clock higher but still get beat in benchmarks.

I guess the best way to put it is that CPU's are designed for specific purposes. I don't believe A12 could scale up and best x86 just the way Atom couldn't scale down and beat it at the same power. Until we see something more than low power ARM chips I don't think anyone will know for sure. I am just of the belief that if it were that advantageous, it would have been done before. I'm sure we will see attempts in the future, but at the moment we just don't know.
 

Thala

Golden Member
Nov 12, 2014
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Until we see something more than low power ARM chips I don't think anyone will know for sure. I am just of the belief that if it were that advantageous, it would have been done before. I'm sure we will see attempts in the future, but at the moment we just don't know.
The done-before argument is not really valid in this case, because you design SoCs for a certain purpose. If the purpose is to put it in a Phone, you would never even remotely consider 1.3V Vcc - in fact you power supply unit would not even support these voltages and required currents.

But as you can read in the article linked by Naukkis if you give the Cortex A72 enough voltage you will pass 4GHz. You dont have to make a chip though, you just need to sign-off the timing (with EDA tools like PrimeTime). In what product would you put a 4GHz Cortex A72 anyway? Remember power goes up by a factor of 4 roughly. (1.2/0.75)^2*(4/2.5) = 4)

Cortex A72 frequency-voltage curve
 
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Thunder 57

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Aug 19, 2007
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The done-before argument is not really valid in this case, because you design SoCs for a certain purpose. If the purpose is to put it in a Phone, you would never even remotely consider 1.3V Vcc - in fact you power supply unit would not even support these voltages and required currents.

But as you can read in the article linked by Naukkis if you give the Cortex A72 enough voltage you will pass 4GHz. You dont have to make a chip though, you just need to sign-off the timing (with EDA tools like PrimeTime). In what product would you put a 4GHz Cortex A72 anyway? Remember power goes up by a factor of 4 roughly. (1.2/0.75)^2*(4/2.5) = 4)

Cortex A72 frequency-voltage curve
Well I seemingly wrongly assumed you were one of those "ARM will take over the world" guys. About 10 years ago even Anand was talking about x86 in iphones. Clearly that never happened. Meanwhile we have had people talking about ARM taking over x86, and that has yet to happen. There was a similar RISC vs CISC debate in the 90's, and we all know how that turned out.

If after 10+ years we haven't seen x86 on mobile or ARM on PC's, I have to think they are both the best at what they do in those form factors. Maybe we will see an ARM uprising within five years, maybe not. I would bet against it though. Sorry if I misunderstood you as an "ARM everywhere" type.
 

DrMrLordX

Lifer
Apr 27, 2000
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Let's not forget the GloFo issues.
True. That was one of the reasons why Rome was shipping (to select partners) so long ago while Matisse was delayed, I imagine. Matisse was originally supposed to be on GF 7nm while Rome was always slated for TSMC.

AMD wisely didn't commit to them by the looks they were able to switch to TSMC. That could have bit them hard but I think it only cost them 1-2 months. Who really knows, though? I expect to see Zen 3 in late August at best to mid October at worst.
July/August seems rational. A lot of it depends on whether TSMC continues to deliver on their nodes in a timely fashion . . . assuming Zen3 is on 7nm+ EUV.
 

Kenmitch

Diamond Member
Oct 10, 1999
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What do you think Skylake or Zen2 can be clocked @0.75V?
Zero, zilch, nothing!

Maybe it's my MB's uEFI or just the way it is. I've run my 3700x all core underclocked to 3.2 GHz @ 0.850v's for some testing without any issues.

Using Ryzen Master selecting anything under 0.800v's it's a instant reboot once applied. Entering bios and doing the vcore over ride option nothing below 0.800v's is available.

Was this a trick question?
 

maddie

Diamond Member
Jul 18, 2010
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True. That was one of the reasons why Rome was shipping (to select partners) so long ago while Matisse was delayed, I imagine. Matisse was originally supposed to be on GF 7nm while Rome was always slated for TSMC.



July/August seems rational. A lot of it depends on whether TSMC continues to deliver on their nodes in a timely fashion . . . assuming Zen3 is on 7nm+ EUV.
Some implied assumptions here.

If the CPU core chiplet is identical on both processes, TSMC 7 & GloFlo 7, then there should not be any delay by using one fab or the other. Are you assuming there were some slight differences between the chiplets from each fab, maybe power/frequency curves, to fully utilize the unique properties effectively? Might the lower than expected clocks on Matisse be caused by this?

If above is close to true, Zen3, AFAIK, was never meant to be fabbed at GloFlo so we might see a bigger increase (IPC + frequency) than expected as all the variants were designed for 7nm+.
 

Paul98

Diamond Member
Jan 31, 2010
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I expect something like a 5-10% bump in performance per clock from architecture changes, a 10% increase in performance from 7nm+, and better overall chip binning, and a top end 16 core chip at 499.
 
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Tuna-Fish

Golden Member
Mar 4, 2011
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If the CPU core chiplet is identical on both processes, TSMC 7 & GloFlo 7, then there should not be any delay by using one fab or the other. Are you assuming there were some slight differences between the chiplets from each fab, maybe power/frequency curves, to fully utilize the unique properties effectively? Might the lower than expected clocks on Matisse be caused by this?
The design rules and cell libraries are entirely different between TSMC and GloFo 7nm. The entire low-level design and debugging phase needs to be redone. That's about 12-18 months of work, assuming sufficient workforce.

Note that I don't believe that anything Zen2 was ever designed for anything GloFo. People assume that major decisions were done when we heard about them or at least not too much before them. I don't think either AMD or GloFo would have winged it, the major decisions were probably made years ago, and Zen2 was always going to be TSMC.
 
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Richie Rich

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Jul 28, 2019
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The done-before argument is not really valid in this case, because you design SoCs for a certain purpose. If the purpose is to put it in a Phone, you would never even remotely consider 1.3V Vcc - in fact you power supply unit would not even support these voltages and required currents.

But as you can read in the article linked by Naukkis if you give the Cortex A72 enough voltage you will pass 4GHz. You dont have to make a chip though, you just need to sign-off the timing (with EDA tools like PrimeTime). In what product would you put a 4GHz Cortex A72 anyway? Remember power goes up by a factor of 4 roughly. (1.2/0.75)^2*(4/2.5) = 4)

Cortex A72 frequency-voltage curve
That's perfect post regarding power consumption. Thanks for that.

Some people has difficulty with understanding the difference between P3 and P4 pipeline and so affecting frequencies (f/V curve). Me as mechanical engineer I have to use always electric->hydraulic analogy. This helps me to understand and imagine the electric processes inside (voltage is pressure, current is mass flow etc).

Those people should imagine this:
  • - every stage of pipeline ......................... . as water channels complex
  • - transistor switching every clock ......... as tsunami wave running in those channels
  • - electron/transistor speed is constant ........ as tsunami wave speed is constant too
  • - critical path ............................................. as the longest possible combination of channels to get to the end of stage (tsunami wave with the longest time to complete) - basicly this limits your frequency because you cannot run next clock/wave before last tsunami is finished. If you do, for example during OC, you get faulty results from logic and your PC crashes. That's why OCed CPU is stable at desktop (not using critical path) and not stable when you run heavy FPU AVX load (using critical path). I think this is the problem of Intel AVX512 down clocking too.


So from above we get:
  • - P4 high frequency architecture has shorter/less complex channels... able to run more tsunamis at time (more freq)
  • - P3 low frequency arch has longer and complex channels... able to run less tsunamis at time
  • - all stages in pipeline should be as eqal as possible in terms of critical paths. This is needed for good power consumption and frequency scaling.

Beside this, to reach higher frequencies you have to adapt memory subsystem too. Typically to keep feeding high freq core you need bigger buffers for uncore because RAM latency is constant.


You can see that ARM cores performance doesn't scale as good as Skylake - due to their design. Apple desktop ARM CPU will need some modifications for high frequency for sure. However those changes are not major IMHO. Apple's 6xALUs design is their key advantage and huge milestone. High freq modification is easy IMHO.

ARM is not taking over x86 desktop because Cortex CPUs are very weak and useless. This will change when powerful ARM CPUs are delivered. Cortex A77 (4xALU) core is comming this year... this might fight with Intel Atom pretty well -> take over whole NAS markets and low cost laptops.
 

DrMrLordX

Lifer
Apr 27, 2000
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The design rules and cell libraries are entirely different between TSMC and GloFo 7nm. The entire low-level design and debugging phase needs to be redone. That's about 12-18 months of work, assuming sufficient workforce.
Exactly.

Note that I don't believe that anything Zen2 was ever designed for anything GloFo. People assume that major decisions were done when we heard about them or at least not too much before them. I don't think either AMD or GloFo would have winged it, the major decisions were probably made years ago, and Zen2 was always going to be TSMC.
I'm not so sure about that. Matisse and Rome share a nearly-identical chiplet design. When GF canned their 7nm, AMD could have just cancelled the GF Matisse design effort and moved Rome chiplets into the Matisse package.
 

NostaSeronx

Diamond Member
Sep 18, 2011
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AMD never had any GF 7LP products besides that one APU that's now on TSMC anyway.
It would be more accurate to say there was no 7LP products. AMD and IBM was apathetic about the 7nm node and NextGen(3nm GAA) at GlobalFoundries.

IBM said they wouldn't give them the product ramp they want.
AMD said they wouldn't satisfy the capacity split (<70% TSMC/>30% GlobalFoundries) in the long run.
March to May 2018 --^

Especially, since GloFo 3.0 is all about switching to FDSOI.
45nm FDSOI RFE/SPCLO
22FDX
12FDX
 
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Tuna-Fish

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Mar 4, 2011
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I'm not so sure about that. Matisse and Rome share a nearly-identical chiplet design. When GF canned their 7nm, AMD could have just cancelled the GF Matisse design effort and moved Rome chiplets into the Matisse package.
Matisse and Rome use the same chiplets. I see no reason whatsoever to believe that they ever would have used different chiplets. It's an insane proposition, much of the value of the chiplet design is getting to use the same cpu chiplet (with super-expensive masks) with many different IO chiplets (with much cheaper masks) to make multiple different products. Matisse was always going to use the same chiplet as Epyc and TR. That chiplet was designed from the start to be on the TSMC 7nm.

"Matisse was supposed to be at GloFo" is just one of those completely unfounded false rumors, that people are trying to fit to data way too hard. It's not true, it was never based in any truth, there never was any reason to believe it was true.

Much like the AdoredTV specs leak, there are still people on this forum claiming it's inaccuracies were just changes made before release. The person who fabricated it and posted it on reddit admitted to inventing it. Yes, it got some things pretty close, but that's just because it was the best effort by a fan to guess what's going to be.
 
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Veradun

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Jul 29, 2016
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Didn't they say they started dual sourcing 7nm products and at some point dropped the ones on GF for obvious reasons?
 

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