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Speculation: Ryzen 4000 series/Zen 3

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I'm sure AMD will pursue IPC and I bet they tried to get similar generational increase for Zen2->Zen3 ,they know what Icelake will be. They cannot afford to waste this chance. It's tricky to go all in again and design for a "new"/improved node (7nm+) while trying to increase IPC and clocks AND core count. So far they managed to do well, we'll see what 2020 brings. My guess : between 10 and 15% IPC increase, more cores, similar clocks (higher ST Turbo).
 
mikk said:
You have really no clue how to do this properly, no wonder. Also your gaming tests are crap as usual from Anandtech because they are bottlenecked from the GPU. Gaming tests in CPU reviews from anandtech are one of the worst in the net, this is a usual anandtech issue, they really can't do proper CPU gaming tests, this is so pointless.
Click to expand...

Andrei makes by far the best cpu reviews on this planet.

I dont agree on the game selection, and to a lesser degree nor the jedec selection, so I head to computerbase.de to see how the cpu does in bf5 1% and can see the 3600 I got for one of the kids is actually faster than the 8700k I am running. I think that shows pretty good what to expect for 2020.

Then I head to AT and read Andreis stuff to learn.

https://www.computerbase.de/2019-07/amd-ryzen-3000-test/3/#diagramm-test-battlefield-v-1920-1080

I am looking forward to plug a ryzen 4000 in the same cheap b350 board. If not well still pretty nice.
 
Hello folks,

Zen3:

1. Yes ... due to EPYC3 backward compatibility with EPYC1 boards.
2. IPC +40% ... 6xALU, 4xFPU-256bit(Zen2), SMT4
3. No increased freq
4. 7nm EUV AKA 7nm+
5. TDP same
6. AVX512 maybe as a support of 2xFPU256bit coop
7. APU on 1H2021


To defend of 6xALU back end - Apple A12 Vortex core has 6xALU and has massive 1.76x IPC INT increase over Intel Xeon SkylakeX:


Code: 
SPEC2006 INT
The Xeon turbos to 3.8 GHz while the A12 “turbos” to 2.5 GHz.

                        Xeon 8176                  Apple A12

    400.perlbench       46.4                       45.38
    401.bzip2           25.0                       28.54
    403.gcc             31.0                       44.56
    429.mcf             40.6                       49.92
    445.gobmk           27.6                       38.54
    456.hmmer           35.6                       44.04
    458.sjeng           30.8                       36.60
    462.libquantum      86.2                      113.40
    464.h264ref         64.5                       66.59
    471.omnetpp         37.9                       35.73
    473.astar           24.7                       27.25
    483.xalancbmk       63.7                       57.03


The most powerful beast CPU on the world in term of INT IPC is running in your cellphone wiht TDP 4.2 Watts. HPC server CPU running @3.8 GHz outperformed by cellphone CPU running @2.5GHz by +12%. Pretty amazing.

+50% ALUs (4->6) deliver +76% IPC over Skylake .... with no SMT at all. Were you worry about utilizing 6xALU? Apple did it. Zen is internaly RISC processor as ARM is, so it's achievable.

SMT4 is not necessary however, Jim Keller knows Alpha EV8 SMT4 design for 20 years. And when you design new CPU because of increased ALUs, you need also new front-end, you can adopt also SMT4. Zen3 might be Jim's the big Zen CPU when he come back to AMD. Assuming that Zen1 was little Zen compromised-but-fast-developed design to avoid AMD's bankruptcy. But I might be wrong.

There is also rumors that ARM is working on desktop/server ARM CPU (and desktop ARM GPU). CPU with probably 6xALUs to keep up with Apple. Intel and AMD have to deliver 6xALU CPU very soon otherwise they are gonna be outperformed by any China company who buy ARM license. I assume they already start working on it when they analyzed Apple A12 Vortex CPU. Well no, 6xALUs brought A11 at 2017. So it's being while already.

Conclusion: I assume that Zen3 might be the first 6xALU x86 CPU just because it is inevitable and Jim Keller had opportunity to do that.
 
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A 40% IPC increase? I could bet a million that won't happen unless you're talking about Zen 1.0. ;-)

The question was what an uplift would be in comparison to Zen 2.0 (Ryzen 3xxx) and I'm pretty sure it will be a single digit figure.
 
Apple has a A11 CPU with 6xALU since 2017.
Development started 2012? Estimated.
Jim Keller started in AMD at 2012, and also working on ARM Zen.
He worked in PASemi and Apple on CPU A4 so he knows people inside.
Engineers talks each other.
There is big chance he knew that Apple is gonna develop 6xALU beast. Why he would develop anything slower than that? So Zen3 might be something even bigger, maybe 8xALU + SMT4, simply realizing the danger of 6xALU ARM in server market. There are so many date and fact coincidences. Just brainstorming and thinking loud.
 
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I agree that Zen 3 is rather likely going to see bigger changes, be it an increase in ALUs, more and/or wider FPUs, SMT4 or something else we haven't mentioned yet. The reason why we should expect that is the fact that AMD (along Keller) planned Zen 1, 2 and 3 all at once, so Zen 3 will be the realization of the envisioned final goal of those first plans, with Zen 1 and 2 just having been stepping stones to get there.
 
2moinmoin: Yes, I agree. Zen1 is about new 4xALU SMT2 design (instead of silly Bulldozer double 2xALU) and hooking up with Bulldozer front-end (which was quite good) and it was already able handle and feed 2 threads. They also kept dual FPU concept from Bulldozer. Zen1 has better gain from SMT2 over Intel and IMHO it is thanks to Bulldozer capability handle two physical threads.

If Zen3 is the Big-Zen-arch-from-scratch (6-8xALU, 4xFPU, SMT4) and design started in the same time as Zen1, they probably decided to create middle step, kind of upgraded Zen1 by features from Zen3. Well that's Zen2, taking Zen3's two 256bit FPUs out of four, fast L1 cache and IO-core-chiplets (without 4GB HBM L4 cache). Well, there is nothing more you can take from big Zen3 6xALU SMT4 design. So Zen1, Zen2, Zen3 could be planned from beginning - Jim Keller's master plan makes sense IMHO. All the puzzles fits pretty well.

The only strange thing is Jim's canceled Zen3 ARM version. I thing this would be killing machine in server market due to missing x86 decoder and much lower power consumption (much more cores in the same socket TDP). Maybe they canceled big Zen3 together with ARM Zen. Maybe they decided to not risk and continue with conservative 4xALU design doing small steps as Intel does. Similar situation as they canceled Jim's big K8 at 1999 (and then Keller left AMD) and keeping 3xALU design until K10 and finish insanity with 2xALU Bulldozer design later on. I'm just worry of consequences of Keller's leave.

At least since Apple's introduction of 6xALU beast in 2017, I'm pretty sure they are working on at least 6xALU design too (to enter market in 2023). Just there is a good chance to have 6-8xALUs beast in 2020 as Zen3.
 
Zen 2 loaded the bases. I'm speculating Zen 3 will hit a grand slam, of course it might just end up being one of those silly inside the park home runs if AMD's launch record strikes again.
 
mohit9206 said:
Why? Am just asking.
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Nothing really, but it's just that I saw that level of detail at this point of the release cycle as worthless. It's not even speculation, in my view, as no supporting evidence or reasoning needed.

In any case, it's your expectation and I should not have depreciated it.
 
My speculation...

The core has hardware level threading, rather than OS level threading. The core can display itself as a single-threaded core to a quad-threaded core.
https://www.semanticscholar.org/pap...-Xue/448e75108b311f71ab99fc1cece85f87caf82db8

With the patent text from IBM being;
"The method may comprise measuring SMT-performance value of a software code, wherein the software code may be executed in a simultaneous multithreading mode by the processor, and measuring non-SMT-performance value of the software code, wherein the software code may be executed in a non-simultaneous multithreading mode by the processor. Additionally, the method may comprise comparing the SMT-performance value with the non-SMT-performance value, and dispatching the software code for an execution mode by the processor depending on the comparison, wherein the execution mode may be selected out of SMT-mode and non-SMT-mode."

Essentially, if the application thread is to heavy it will go 1T, if the applications thread is light it will move to 2T and accept another thread, so on. It is done through a predictive device, like branches, but instead for threading.
 
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mohit9206 said:
Do you guys think that Ryzen 4600 will still be 6C/12T or will it be 8C/16T ?
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Is it about the number for you? Or rather about the price point?
3600 is around $200, though the upcoming 3500 appears to have 6 cores as well so we'll see how low that one's price will go. If Ryzen 4k significantly increases IPC again while not increasing the amount of cores I'd expect the model numbers as well as the prices to stay similar.
 
yes

this.

small_amd_zen_family.jpg
 
zrav said:
Is there reason to believe that the Ryzen 4000 series will already be Zen 3 and not Zen 2+ ?
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2zrav: There is some rumors that Zen2 process 7nm is not compatible with 6nmEUV. Zen3 7nm EUV is shrinkable down to 6nmEUV. So if some plus variant will happen, it's gonna be probably Zen3+. We have confirmed Zen3 server CPU Milan in mid2020 - Zen3 is coming soon. There is no space for Zen2+.


2NostaSeronx: That's quite interesting. I agree that there could be several strategies how to handle SMT4, you can also change a priority for each thread on SMT4... however not sure how long would it take to be adopted by MS scheduler.
 
Richie Rich said:
2zrav: There is some rumors that Zen2 process 7nm is not compatible with 6nmEUV. Zen3 7nm EUV is shrinkable down to 6nmEUV. So if some plus variant will happen, it's gonna be probably Zen3+. We have confirmed Zen3 server CPU Milan in mid2020 - Zen3 is coming soon. There is no space for Zen2+.
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TSMC N6 (not EUV) is derived from TSMC N7 and therefor allows a shrink using a compatible PDK (not zero work to port, but low effort comparatively). TSMC N7 and N7+ (EUV) use different PDKs (product development kits, design rules, etc.) - so it's a medium to high effort to port. Since Zen 3 will have many changes to Zen 2, it is a full out development project - not easy at all. Hopefully, N7+ will not lead to any clock reductions.
 
Ajay said:
TSMC N6 (not EUV) is derived from TSMC N7 and therefor allows a shrink using a compatible PDK (not zero work to port, but low effort comparatively). TSMC N7 and N7+ (EUV) use different PDKs (product development kits, design rules, etc.) - so it's a medium to high effort to port. Since Zen 3 will have many changes to Zen 2, it is a full out development project - not easy at all. Hopefully, N7+ will not lead to any clock reductions.
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Thanks Ajay for explanation. So Zen2 could have a die shrink too if they need that. Maybe for APU.

If clock reductions happen, and Norrod was mentioned that, the only possible way how to increase performance is to develop high IPC uarch. I think we can expect some very exciting CPUs in next 2-3 years. Also desktop battle between Apple ARM iMac vs x86 will be interesting.
 
All this talk about Jim Keller... was really THAT important on Zen and future iterations? Wasn't his principal role just to manage the project while others did the real work?
 
A/// said:
This is what I've read, too.
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If I remember correctly, the brains of the operation was Mike Clark with Jim Keller acting as the team manager. Jim helped bring focus and expertise to AMD but the heavy lifting was largely done by Mike Clark and his team.

To throw my hat into the ring:
  1. Will it support currently existing motherboards (300/400/500 series chipsets)?
    • Yes, in the same fashion to the Ryzen 3000 series.
  2. What kind of IPC increase are we talking about?
    • Depends what AMD does with their 18% extra density from TSMC 7nm+, but in looking at AT's articles on the Zen 2 and Sunny Cove microarchitectures, Zen 2 is weaker in dispatch width, number of AGUs and load/store bandwidth (memory-subsystem, basically), and re-order buffer size. Where Zen 2 is strong is in the size of it's micro-op and L3 cache, on-die fine-grained energy and turbo boosting algorithms, and it's performance/die size efficiency. I think if Zen 3 needs to catch up to Sunny Cove, AMD should fatten up the memory-subsystem since it appears there's plenty of execution units; what's lacking is keeping the execution units fed and getting the data on and off die.
  3. Will AMD manage to squeeze more frequencies?
    • No, I think they will tap into 7nm+ to improve perf/W by keeping frequencies the same but using the power budget to implement architecture improvements that improve IPC.
  4. What node will it use?
    • TSMC 7nm+
  5. What will be its TDP?
    • Same as Zen 2: 65W/95W/105W for mainstream desktop.
  6. Will it support AVX512 instructions?
    • Yes, but will execute AVS512 code at half-rate. I think AVX512 will be executed at full speed only when Zen transitions to TSMC or Samsung's 5nm-class nodes, where they will have the transistor and power budget to implement AVX512.
  7. When and if we can expect Ryzen 4000 CPUs with modern onboard graphics (e.g. Navi10/Navi20)?
    • On-board graphics? Like on the motherboard? Never. If you mean on the same die, then it will be in the form of an APU using Zen 2 with either Vega or Navi on TSMC's 7nm node and probably will arrive next year.
 
AVX512 support will cause so many headaches once AMD has it running full-speed. At least AMD isn't using an offset, so you won't necessarily get massive downclocking from running AVX512 in a VM.
 
Ajay said:
TSMC N6 (not EUV) is derived from TSMC N7 and therefor allows a shrink using a compatible PDK (not zero work to port, but low effort comparatively). TSMC N7 and N7+ (EUV) use different PDKs (product development kits, design rules, etc.) - so it's a medium to high effort to port. Since Zen 3 will have many changes to Zen 2, it is a full out development project - not easy at all. Hopefully, N7+ will not lead to any clock reductions.
Click to expand...

I also remember seeing one of TSMC's info mentioning N7+ provides an easier mirgation path to N5 because N5 is based on N7+.
 
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