This is covered in the Q&A i posted, each core can write or read 32 bytes a cycle to the L3 cache (which ever way it hashes). each slice of the L3 has a buffer ( so multiple core can write to the same L3 slice each cycle). it is unclear if each slice can read and write 32 bytes a cycle or just read or write 32 bytes a cycle.t is unclear how large of a chunk is interleaved between caches. Byte interleave seems too small. Perhaps a 32 byte cache line is interleaved across the 4 slices. They have shown slides with 32 bytes a cycle. That would be 8 bytes/64-bits from each cache slice. It is also unclear what you think a “link” is.