Speculation: Ryzen 4000 series/Zen 3

[moinmoin]

Is it because of the process or the design?

Probably both, the process doesn't improve power usage sufficiently and may have a worse frequency/power curve, while the design clearly is not optimized for that node. AMD warned before that getting high frequencies is harder on smaller nodes. N7 seems to handle it well, N5 may take more time to reach a similar level.

no one posted this ?

https://twitter.com/i/web/status/1321442583348916224

latency looks alright

Hm, looking around for similar CPU/RAM frequencies memory read is essentially the same as Zen 2, latency down ~5ns. L1 and L2 cache bandwidths are hugely improved, look like nearly 3 times that of Zen 2 which points to Zen 3 cores having its Load/Store redesigned to match (and surpass?) what Intel was offering all along. L3 cache bandwidth seems that of a single chiplet Zen 2 chip, but improved between ~6% (read) and ~26% (write).

 

[IntelUser2000]

L1 and L2 cache bandwidths are hugely improved, look like nearly 3 times that of Zen 2 which points to Zen 3 cores having its Load/Store redesigned to match (and surpass?) what Intel was offering all along. L3 cache bandwidth seems that of a single chiplet Zen 2 chip, but improved between ~6% (read) and ~26% (write).

Not according to that screenshot. The throughput is exactly the same as Ryzen 3000 series and also Skylake.

Icelake is higher, and the highest is Skylake-SP.

 

[moinmoin]

Not according to that screenshot. The throughput is exactly the same as Ryzen 3000 series and also Skylake.

Icelake is higher, and the highest is Skylake-SP.

Maybe we are looking at different screeshots. I was comparing the tweeted screenshot mainly with this one shared on TPU's forums, matching memory clock (though better subtimings):

 

[JoeRambo]

Maybe we are looking at different screeshots. I was comparing the tweeted screenshot mainly with this one shared on TPU's forums, matching memory clock (though better subtimings):

3600 chip is 6 core, 1500/6*16 => 4000GB/s for 16C

 

[Tuna-Fish]

Wow, L3 bandwidth got cut in half, i guess that explains lack of MT scaling in benchmarks. Not exactly unexpected due to move from 2 to 1 L3 domain and end result is that 8C can access ~same L3 BW as Intel Skylake 8-10C ring.

Wow, there are probably only 4 L3 slices per chiplet. If they are all still 32B/cycle, that would explain the total throughput. Would simplify the routing, and reduce the amount of links needed...

 

[obidamnkenobi]

5800X CPU-Z 650 Single-thread & 6593 Multi-thread scores

Is this legit? That performance jump seems insane! I can take my current CPU and jump 4 generations, and barely see an increase of a few points/percent. Yet Ryzen 5000 is supposedly ~20-30% greater then just a gen earlier?!

 

[inf64]

Is this legit? That performance jump seems insane! I can take my current CPU and jump 4 generations, and barely see an increase of a few points/percent. Yet Ryzen 5000 is supposedly ~20-30% greater then just a gen earlier?!

It's possible especially in some select benchmarks. ST IPC is ~19% better on average vs Zen2, that is massive jump and what we could call a true gen to gen leap.

Regarding the MT performance and the reasons why it might not reflect the full 19% (in some cases), it doesn't really matter. AMD has such a massive MT (throughput) advantage over intel that it's not even funny anymore. The only benchmarks in which intel has some advantage will be AVX512 and that is like 1% of the workloads (if that).
Zen3's competition in MT workloads is Zen2 which is considerably slower - so all is good.

AMD now has a better chip in every segment, with higher IPC (Zen3) cores and higher core counts. Zen4 can just get the MT throughput to another level, with more cache, more chiplets and even more IPC. Intel will need Golden Cove cores with the same core count and same clock speeds to even stay on the same level as Zen4 cores and we know this will not happen as per their latest roadmaps. So relax, MT performance is great as it is and ST is the best in class. AMD is in a great place and I hope they keep their foot on the gas.

 

[DisEnchantment]

Probably both, the process doesn't improve power usage sufficiently and may have a worse frequency/power curve, while the design clearly is not optimized for that node. AMD warned before that getting high frequencies is harder on smaller nodes. N7 seems to handle it well, N5 may take more time to reach a similar level.

Not only this, also the scaling is not ideal, logic, SRAM, SerDes, Analog blocks etc scale differently. And a CPU is not all logic.

Apple’s A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC’s Density Claims

Our friends over at ICmasters have delved into the package of the Apple A14 Bionic. The die size has been unmasked, and it stands in at 88mm2. Despite cramming in 11.8 billion transistors, the die …

semianalysis.com

I am still hopeful of Samsung GAA to bring back some of the gains like we saw when moving to FinFET.

 

[IntelUser2000]

3600 chip is 6 core, 1500/6*16 => 4000GB/s for 16C

This.

L1 Write
2266GB/s for 5950X
766GB/s for 3600

L2 Read/Write/Copy
~2080GB/s for 5950X
720-760GB/s for 3600

5950X: 4.94GHz with 16 cores
3600: 4.167GHz with 6 cores

Clock and core normalized bandwidth

L1 Write
2266GB/s for 5950X
2421GB/s for 3600

L2 Read/Write/Copy
~2080GB/s for 5950X
2276-2402GB/s for 3600

It hasn't improved one iota for Zen 3.

 

[moinmoin]

3600 chip is 6 core, 1500/6*16 => 4000GB/s for 16C

Thanks for the correction. Somehow I was thinking L1 and L2 cache bandwidth would be given as per core, not as a sum across all cores which is frankly nonsensical... ah well.

 

[IntelUser2000]

Thanks for the correction. Somehow I was thinking L1 and L2 cache bandwidth would be given as per core, not as a sum across all cores which is frankly nonsensical... ah well.

Some tests give it per core.

 

[Kenmitch]

no one posted this ?

https://twitter.com/i/web/status/1321442583348916224

latency looks alright

Latency doesn't look bad, but those timings are pretty loose. It will be interesting to see what it looks like with some better ram.

 

[Det0x]

no one posted this ?

https://twitter.com/i/web/status/1321442583348916224

latency looks alright

For comparison, this is my PBO 3950x at 3666mhz with very tight timings



*edit*

ClockTurner OC (static clock)

 

[Carfax83]

For comparison, this is my 3950x at 3666mhz with very tight timings

A 5950x with similar timings should easily get in the mid to low 50s, which is very good for not having an IMC.

 

[moinmoin]

A 5950x with similar timings should easily get in the mid to low 50s, which is very good for not having an IMC.

Dropping images or links without your own commentary is not allowed.


esquared
Anandtech Forum Director

 

[Carfax83]

^^ LOL! When I said it doesn't have an IMC, I meant in terms of how it compares to Intel's IMC. Correct me if I'm wrong, but Intel's IMC is located on the same die as the CPU cores in a monolithic design (which is why they have such low latencies), whereas with AMD's chiplet design, the memory controller is on a separate 12nm I/O die located on the same piece of silicon, connected by infinity fabric connection.

So technically, AMD is using an IMC, but not in the same manner as Intel.

 

[richierich1212]

SiSoft publishes 5800X review

SiSoft 5600X review

There’s also scores for the 5950X.

 

[LightningZ71]

That SiSoft review is almost glowing. The praise is so effusive that it borders on disbelief. Impressive!

 

[thigobr]

Impressive indeed! Cannot wait for next week!

Quote from the review:
It seems that there’s nothing stopping Zen3!

 

[cortexa99]

I don't know if it has been posted before:

Exclusive Benchmarks - Google Drive

docs.google.com

2			Cinebench R20 (higher is better)				Cinebench R15 (higher is better)				CPU-Z (higher is better)			Passmark Single Threaded (higher is better)			Passmark PerfTestv10 (Higher is better)
3			Multi core	Single Core			Multi core	Single Core			Single Thread	Multi Threads	R5 5600x	3487			CPU mark	Integer Math	Floating Point Math	SSE	Encryption	Sorting	Cross-platform
4		R5 5600x	4117	600		R5 5600x	1780	253		R5 5600x	642.7		R5 3600x	2677		R5 5600x	22403	77596	40890	16293	16007	27596	43596
5		R5 3600x	3751	501		R5 3600x	1647	204		R5 3600x	505		i5 10600k	2926		R5 3600x	18318
6		i5 10600k	3629	501		i5 10600k	1615	215		i5 10600k	551		i5 10900k	3177		i5 10600k	14594
7		i5 10900k	6399	539		i5 10900k	2677	234		i5 10900k	584		R9 3950x	2747		i5 10900k	24283
8		R9 3950x	9148	531		R9 3950x	3897	217		R9 3950x	524					R9 3950x	39281
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