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Speculation: Ryzen 4000 series/Zen 3

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maddie

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Booking means to place orders. Fully booked implies all wafers are booked. I've used fully booked when phrasing Apple until today when that Digitimes article came out. Digitimes previously reported Apple would be using 3nm (or 2nm) in late '22 or mid '23, and I suspect for something due for a refresh then.
Yeah but AMD is not following after 2021. They will be following after 2020.
 

Kenmitch

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Oct 10, 1999
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Yeah but AMD is not following after 2021. They will be following after 2020.
Earlier this year there was mention of a enhanced 5nm node for AMD with a estimated 20,000 wafers per month in late 2020. It wasn't specific it was AMD only, but what became of it?
 

NostaSeronx

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Sep 18, 2011
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Earlier this year there was mention of a enhanced 5nm node for AMD with a estimated 20,000 wafers per month in late 2020. It wasn't specific it was AMD only, but what became of it?
Actually, it was mid-2020 being June.

AMD High-end GPUs have been switched from 7nm to 5nm and has started to use the vacated 24,000 N5 wafers per month from Hisilicon. <== Essentially, the June bomb.

https://money.udn.com/money/story/5612/4620238 :: 30,000 for N5P came from this: 2020-06-08
http://www.techweb.com.cn/world/2020-06-22/2794668.shtml :: 20,000 for N5 came from this: 2020.06.22
Hisilicon share = up to 24,000 per month
Apple share = up to 15,000 per month

and the Ryzen rumor is done by A/// below me => 2020.4.14
 
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A///

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Feb 24, 2017
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Earlier this year there was mention of a enhanced 5nm node for AMD with a estimated 20,000 wafers per month in late 2020. It wasn't specific it was AMD only, but what became of it?
Err no. There was never confirmation about that. That was a PCGamer article that got picked up by VideoCardz and Wccftech, IIRC. The original claim came from a Taiwanese news article on the Chainnews site. I think they're Taiwanese.

The claim was that TSMC developed a special enhanced 5nm node for AMD. Same article stated AMD needs no more than 20K WPM at a 12" size. Same article stated NVidia increased their 7nm order. We know that GeForce cards and quite possibly Quadros are on 8nm at Samsung, and their DC products may very well be on 7nm at TSMC.


I think it was a poorly written article because TSMC wouldn't spend that kind of research on AMD alone. I'd say it's an enhanced node meant for high performance computing because Apple is a very likely candidate to use that same node. This article was published before Apple Silicon was dropped on the world during Apple's June's event. Just as there's multiple 7nm nodes I expect the same for 5nm. If today's release I posted earlier is true than @jamescox shoots up to the top in all our theories because it is the most viable and easy way for AMD to switch to a new tech stack and not also worry about an accompanying node shrink at the same time. This is not new news IMO as AMD would have have been told in advance of these things by TSMC. If Warhol is a legitimate product, then it's on 7nm per the leaks by MebieuW and uses DDR5, USB4, PCIe5 (maybe). I think more SATA capability will be a thing for higher end creator boards, especially TR. It'll be on the AM5 socket. Raphael is 5nm and is supposed to come along in '22 according to the same leak. It should be a node shrink and a performance improvement assuming the Warhol doesn't get a performance boost. By the time Raphael comes out, the majority of bugs if any will be worked out and it should be a smoother transition.

My PCIe theory only works because there's always been a 1-2 year gap between a standard being finalized and approved and it being available in products. PCIe4 was finalized in June 2017, and available on Ryzen 3000/X570 then later the B550. At the very end of May 2019, PCI SIG finalized PCIe5. Assuming the 2 year gap is standard chances are high we'll see it with "Warhol" if it's real.

@jamescox's theory makes more sense than mine or DrMLord... I can't remember his username. Though as James pointed out, there's some complexity involved with possible stacking on Zen 4... Given everything this year and it still being "summer" weather in a lot of places we've all gone a bit stir crazy, especially having to wait on our hands and feet for the October 8th announcement, and of course, the October 28th announcement. Frank Azor doesn't help much either!

 
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Shmee

Memory and Storage, Graphics Cards
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Weren't those largely dependent on silicon lottery as opposed to having an easy 500-700 Mhz OC room?
Silicon lottery always applies, but I believe most of these would do 4.2GHz+. My 3770k I had would do 4.4GHz+, my 5930k 4.4GHz, and my Xeon E5 1660 v3 4.3GHz. Even my 4930k QS would do 4.1GHz.
 

A///

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Feb 24, 2017
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Silicon lottery always applies, but I believe most of these would do 4.2GHz+. My 3770k I had would do 4.4GHz+, my 5930k 4.4GHz, and my Xeon E5 1660 v3 4.3GHz. Even my 4930k QS would do 4.1GHz.
Oh. I did like four Ivy builds for people and found them highly varied in what they could do. One chip was so bad it wouldn't clock past 4 Ghz. I ended up exchanging it. I won't name the store, but they were always generous with that kind of thing with return customers and enthusiasts. I never got my hands on -Es. They were always either sold out or were bumped up in price.

I'm going over what I'll do with my Ryzen build. I might get that BeQuiet 360 mm cooler they advertised this week. I've got a few cases in mind that focus on bringing in cool air. I'm on WFH indefinitely pending changes.
 

jamescox

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Nov 11, 2009
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So first half of your post. Forget it! Remember what started this conversation? Well, it now appears there's a new rumor by someone who's actually credible, at least for graphic cards. Some dude named Yuko posted the following:



HBM2e was something that crossed my mind but I didn't think AMD would increase costs in such a manner. Still, another 1.5 months til that announcement, or close to that.

As for the IO die. Technically you don't need stacked chiplets. All you do is move model names around. If Yuri's leak is anything to go by, Zen 4 may see something like this if using the Ryzen 5000 namesake.

Ryzen 5600X: 8/12
Ryzen 5800X:10/20
Ryzen 5900X:12/24
Ryzen 5950X:16/32

Just an idea. They can move around the processors. What they'll do with chiplets that have 3 viable cores each.. IDK. Value bin options? TR can follow suit but you need to trim the fat down. Again, just an idea here.
A full interposer is kind of expensive for a gaming card. It also seems like we would have seen more info about a full interposer HBM card, if it is launching in October. It might be possible that they are using some non-interposer chip stacking tech. I have not had time to read up on what TSMC has available, but it is actually possible that both rumors are true.

I have read a bit about Intel EMIB. EMIB is essentially taking a die, flipping it over, and embedding it in the package under two other die. This allows micro-bumps to be used, similar to a silicon interposer, without the cost of a full interposer with TSVs. It is a lot less silicon and a lot less processing due to no TSVs. It should be much cheaper than a full interposer and is much smaller since it only goes under a small portion of the other die and it can be almost a standard flip-chip, except with micro-bumps.

I know TSMC has some competing tech, but I haven't had time to read up on the specifics. If you have something similar to EMIB, then there is no reason for the "upside down" die to be just interconnect. They could put something on that die, like maybe 128 MB of cache. This could lead to a situation where you have a 128 MB SRAM cache, a single stack of HBM, and still have some GDDR6 to back it up. That would be very weird, but may keep cost down. I guess I need to read up on TSMC chip stacking tech to get an idea if such a thing is plausible in the current time frame. I didn't expect much chip stacking until Genoa, but AMD has been using interposers for a while now with GPUs. It may be plausible that they are now taking advantage of other chip stacking tech for GPUs.

I have no idea what emulation mode would mean, but it sounds like AMD may have some far outside the box solution. It will be disappointing if it is just a standard GDDR6 gpu for the mid to low end and a standard HBM gpu for the high end.
 

Shmee

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Oh. I did like four Ivy builds for people and found them highly varied in what they could do. One chip was so bad it wouldn't clock past 4 Ghz. I ended up exchanging it. I won't name the store, but they were always generous with that kind of thing with return customers and enthusiasts. I never got my hands on -Es. They were always either sold out or were bumped up in price.

I'm going over what I'll do with my Ryzen build. I might get that BeQuiet 360 mm cooler they advertised this week. I've got a few cases in mind that focus on bringing in cool air. I'm on WFH indefinitely pending changes.
Hmm well with IvyBridge, is when intel first went away from soldered to using cheap TIM. I remember the first 3770k I bought was a return that was ruined as someone had de-lidded it improperly. It was not marked as returned though lol. I remember it not posting, then when I checked the CPU, its top came off LOL. So I returned it to Fry's and told them not to put it back on the shelf again.

That said, 3770k had higher IPC over sandy, as well as PCIe gen 3, and still OCed pretty well in my experience.
 

uzzi38

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Oct 16, 2019
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A full interposer is kind of expensive for a gaming card. It also seems like we would have seen more info about a full interposer HBM card, if it is launching in October. It might be possible that they are using some non-interposer chip stacking tech. I have not had time to read up on what TSMC has available, but it is actually possible that both rumors are true.

I have read a bit about Intel EMIB. EMIB is essentially taking a die, flipping it over, and embedding it in the package under two other die. This allows micro-bumps to be used, similar to a silicon interposer, without the cost of a full interposer with TSVs. It is a lot less silicon and a lot less processing due to no TSVs. It should be much cheaper than a full interposer and is much smaller since it only goes under a small portion of the other die and it can be almost a standard flip-chip, except with micro-bumps.

I know TSMC has some competing tech, but I haven't had time to read up on the specifics. If you have something similar to EMIB, then there is no reason for the "upside down" die to be just interconnect. They could put something on that die, like maybe 128 MB of cache. This could lead to a situation where you have a 128 MB SRAM cache, a single stack of HBM, and still have some GDDR6 to back it up. That would be very weird, but may keep cost down. I guess I need to read up on TSMC chip stacking tech to get an idea if such a thing is plausible in the current time frame. I didn't expect much chip stacking until Genoa, but AMD has been using interposers for a while now with GPUs. It may be plausible that they are now taking advantage of other chip stacking tech for GPUs.

I have no idea what emulation mode would mean, but it sounds like AMD may have some far outside the box solution. It will be disappointing if it is just a standard GDDR6 gpu for the mid to low end and a standard HBM gpu for the high end.
InFO_MS first comes to mind for an interposer-less 2.5D stacking tech. But my understanding was it's for way smaller dies, not anything even close to 505mm^2 from the marketing slides.
 
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Ajay

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The claim was that TSMC developed a special enhanced 5nm node for AMD. Same article stated AMD needs no more than 20K WPM at a 12" size. Same article stated NVidia increased their 7nm order. We know that GeForce cards and quite possibly Quadros are on 8nm at Samsung, and their DC products may very well be on 7nm at TSMC.
Well, from the article you quoted
But the piece also goes on to say that: "TSMC is said to have developed a 5nm enhanced version of its process specifically for AMD, which has a capacity requirement of no less than 20,000 12-inch wafers per month."
The advanced node still relies on the same tooling as 5nm (hence the competition). A couple of masks may be different to to build out larger/less dense xtors with a higher drive current that would allow faster switching. Other, smaller, vendors may use the same node (5NP). Whatever the case, 240K wafers per year is a large enough order for TSMC to modify it to meat AMD's needs (that's what, a couple Billion dollars+ in revenue).
 

A///

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Feb 24, 2017
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The advanced node still relies on the same tooling as 5nm (hence the competition). A couple of masks may be different to to build out larger/less dense xtors with a higher drive current that would allow faster switching. Other, smaller, vendors may use the same node (5NP). Whatever the case, 240K wafers per year is a large enough order for TSMC to modify it to meat AMD's needs (that's what, a couple Billion dollars+ in revenue).
I know how nodes work. I was pointing out how it was framed that AMD would be the only high performance customer. Which given the estimates of wafer costs thrown out there earlier this week would justify your statement ending your post. Except why would TSMC stop there, especially if it meant getting more customers in on it. May even cost more per wafer. If the performance is genuinely better on this node variant, and if it does exist (I don't remember there being confirmation of it by TSMC), then it would be wise to get as many customers on it who'll directly benefit from the performance it gives. Though we're over a year away from Raphael being on 5nm. It's kind of useless to talk about it now. We know Apple booked a lot of 5nm. It never got into specifics, but I assume it's a mix of the two known nodes if this high performance 5nm is legitimate.

Make sense? In any case, I think Apple would be the other customer if true. If had to take a wild guess, it'll be the AS for their computers and possibly the A14X or Z. I think the Z is the computer variant and the X is the iPad Pro. I don't really follow Apple stuff myself. If Warhol real, then the timelines add up if you take James' theory into account.

If I felt more confident about it, I may wait to jump on that instead but I should know better than to dive head first into new hardware at this point in my life.
 

french toast

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Feb 22, 2017
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Yea I believe next Gen IOD will be 6nm and will debut on warhol Q3 2021.
I also believe that 19H family will be capable of SMT4.. so technically available from Zen 3...but not enabled until Zen 3+ warhol or Zen 4.
I also believe we will see a dramatic FPU change at Zen 4 on N5P - Q3 2022.

Zen 3 = Same core counts, SMT 2, AVX 256 (hopefully some combined opps for AVX 512 speed up), 5ghz Single core turbo, - 15-20% IPC.

Zen 3 architecture laying down the groundwork for some big features for Zen 4 imo, even if we don't see them.
 

jamescox

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InFO_MS first comes to mind for an interposer-less 2.5D stacking tech. But my understanding was it's for way smaller dies, not anything even close to 505mm^2 from the marketing slides.
Looking at the anandtech article:


It looks like CoWoS-L is what they would want, although some of the InFO stuff looks very similar. There is a slide there showing the cross section for CoWoS-L. It has a thinned silicon die embedded in the package substrate that has a small part under the ASIC and extends partially under the HBM stack to connect them without using a giant silicon interposer under everything.

This seems to be TSMC’s equivalent to Intel EMIB. The embedded die can be active or passive, so it could contain cache or other circuitry instead of just metal interconnect. Power consumption might be an issue if they put that much in the embedded die though. The embedded die doesn‘t seem like it would have applications outside of GPUs with HBM. I don‘t see how it could be used for Epyc, so this should be in the RDNA 2 speculation thread.

The SoIC tech is probably what they would use for stacking cpu die. It has better thermal performance than tech with micro-bumps. I suspect that initial Zen 3 will look exactly like Zen 2 package. If there is a Warhol, it might have the IO in some kind of stacked configuration that would share some components with Zen 4 coming later. I have no idea how they would do that though.
 

DisEnchantment

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Mar 3, 2017
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InFO_MS first comes to mind for an interposer-less 2.5D stacking tech. But my understanding was it's for way smaller dies, not anything even close to 505mm^2 from the marketing slides.
InFO has some drawbacks like seen on the Pro RX5600M for Apple. It is not suitable for high performance operations, in terms of thermals and frequency due to the nature of the bonding of the micro bumps. But it is a lot thinner.
CoWoS is what I think it would will be. Reasonably cheap, being mature and in use by every one in HPC space who are fabbing at TSMC.
 

jamescox

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InFO has some drawbacks like seen on the Pro RX5600M for Apple. It is not suitable for high performance operations, in terms of thermals and frequency due to the nature of the bonding of the micro bumps. But it is a lot thinner.
CoWoS is what I think it would will be. Reasonably cheap, being mature and in use by every one in HPC space who are fabbing at TSMC.
I don't know if the CoWoS-L variant is available now; it is sounding more like a 2021 product. Some of the InFO tech has been available for a while. A mobile part may not be representative. They aren't going to waste power by clocking it higher than necessary to supply the size of GPU used. It they are using HBM2e in RDNA2, then they are going for high clocks. Any kind of HBM or cache would probably be in the gpu package, even if it is just a separate chip connected by infinity fabric serdes links. A multi die package may have a lid on it, so it is possible that the gpus just look like 256-bit GDDR6 interfaces from the outside, even with the cooler off. I don't think we are going to know anything for sure until the launch. The October 8 launch may just be Ryzen 5000, but not Epyc Milan. Even if some tech in RDNA2 GPUs is applicable to Epyc, it would be unlikely to be used in Ryzen processors, so we probably do not get any info about it on October 8. Ryzen 5000 sounds like it wil be a big upgrade without any weird cache chip or other special sauce.
 

DrMrLordX

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Milan and Vermeer will be competing?
Yeah, the dice will come off the same wafers. So if AMD has limited orders of N7+ (which inevitably they will; they can't order infinite wafers) and Milan demand ramps up, then anything that bins well enough for in-demand SKUs will go there first. If Milan sells too well or has too much pent-up demand before release, Vermeer supplies will suffer. By how much, we don't know.

Probably? Are we just pulling random facts out of nowhere now? What does probably mean to you? Finished validation? Taped out? Packages? Awaiting binning? Packaged and set for retail?
Packaged and set for retail. And it's mostly based on early UEFI revs, and how many of them popped up in OEM repos once x570 launched. Turned out AMD had all manner of interesting UEFI revs and AGESA versions kicking around before July 7th 2019, including some that had to be crippled to mess with leakers.

5nm was already debunked by the Digitimes article translation I posted. Apple has booked 5nm throughout 2021, with AMD to follow first thereafter, at least that's how I've interpreted it.

If Warhol is real, it's AM5 with DDR5 and USB and possibly PCie5 since that is ready to go.
Others have already addressed this point, but if AMD really wants 5nm for hypothetical Warhol, they could probably get it done if their launch date is late H1 2021. It would certainly be easier for them to stick with N7+.

What makes you think there will be many early adopter bugs?
Matisse had them, and Summit Ridge also had them. With Matisse, it was mostly AGESA-related.

Current DDR4 speeds are fine, especially if you can get your hands on good 3200 RAM and OC it.
They are, but at the same time, we're kind of stuck. Micron and Hynix made significant advancements with e-die and CJR respectively, but Samsung isn't pushing A-die or M-die into the DiY market. Samsung b-die is still the cream of the crop when it comes to enthusiast performance, and it has been for a very long time. We should be seeing enthusiast A-die by now (in improved density no less) but we aren't. I suspect everyone is waiting for DDR5 to push performance memory products.

DDR5 is going to be new, problematic, low speed, very high cost. You overstimate the early adopters here. DDR5 will be much more expensive than early DDR4 was by a longshot.
I'm sure DDR5 will be expensive. But slow? I'm not so sure. DDR5 will jump to 5200 pretty quickly, and if AMD has an IMC (and IF) that can go there in Warhol and/or Raphael, it'll be a heck of a thing to see.

Erm, what? AMD began being complacent years before that, not seeing Core 2 as a threat.
Core2 launched in 2006. 2005 was the critical period where AMD could have/should have responded by moving past K8. Ruiz infamously dismissed the threat, choosing instead to believe that Intel would stay with Netburst.

You're comparing a then complacent AMD with a totally different management system compared to now.
Why not? The current management team isn't the same as in 2017, at least in terms of behavior. Same people, different actions. I think AMD is getting complacent. They might have much better reason to be so this time around - Intel is really struggling on the tech front. But I would rather they were a bit more paranoid ala Andy Grove. Also AMD really needs to continue punishing Intel with crushing benchmark wins in critical areas where Intel makes their money. Intel is making bank off bad tech. Rome hasn't moved the bar far enough. The sooner they can iterate through Milan to Genoa, the better. AMD has to chase that marketshare and mindshare. In the end, what we all need them to do is overtake Intel and then be a fundamentally better, more consumer-friendly company once they are sitting on top.

As a consumer, I don't think it's unreasonable to expect AMD to remain a technology-focused company that caters to the growing demands of users while making a healthy profit in the process.

Intel has got nothing viable at least for a few more years.
I think I was pretty clear in indicating that already. You're not exactly disagreeing with me.

You've been waiting 15 months and you're literally throwing toys around saying AMD is flawed
Throwing toys? Oh come now.

and they're soon to meet their demise because it seems like 2005-2006 is repeating itself.
Learn to read. I never said they would meet their demise. It's just that they are getting complacent, and soon that will lead to them being greedy. And if someone doesn't challenge them, they'll become the next Intel: rehash products, raise prices, squeeze consumers, etc. We need AMD to stay on a competitive footing at least so they'll keep their focus on continued advancements of technology irrespective of whether another company can seriously compete with them. That's what the semiconductor game has been about in the past, and that's what it should be about in the future until the laws of physics finally say "no". And we aren't there yet.

Ryzen "Raphael" is a 5nm chip...
Yes, but TSMC has been known to produce multiple iterations of nodes at the same general feature size. For example:


That gives them N5 and N5P? At least? So Raphael could be N5P while Warhol could be N5.
 

A///

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Yeah, the dice will come off the same wafers. So if AMD has limited orders of N7+ (which inevitably they will; they can't order infinite wafers) and Milan demand ramps up, then anything that bins well enough for in-demand SKUs will go there first. If Milan sells too well or has too much pent-up demand before release, Vermeer supplies will suffer. By how much, we don't know.
This was me pointing out the absurdity of your post. It has always been that way. The best performing chiplets in terms of clock and not being power hungry are going to Milan/Epyc. You don't need the high clocks for Epyc either. You even pointed out yourself they could have been taped out months ago and AMD is milking Zen 2. One day you say that, the next day you say they'll be capacity constrained, and then you go back to your original point.

Packaged and set for retail. And it's mostly based on early UEFI revs, and how many of them popped up in OEM repos once x570 launched. Turned out AMD had all manner of interesting UEFI revs and AGESA versions kicking around before July 7th 2019, including some that had to be crippled to mess with leakers.
That date period only refers to people who went deep diving into revisions. You keep mixing up your reasoning here. AMD was never capacity contained last year in July. They admitted they heavily underestimated the number of sales they would have on the 3900X. The 3900X was never a paper launch, nor was the 3950X.

IC: From our audience, one of the most common questions I need to put to you is about TSMC’s capacity. Can you shed some light into how this might affect AMD?


MP: TSMC is a key partner for us, and they were with us at our second generation EPYC launch. I think that really helped people to understand the scale that TSMC has. The most rapid launch in the history of TSMC was its 7nm process node, which has had an asymptotic volume ramp and that was well ahead of our launch of Rome and EPYC. So we’re getting a great partnership with TSMC, as well as great supply. We did have some shortfalls on chips when we first launched our highest performing Ryzens, and that was simply demand outstripping what we had expected and what we had planned for. That wasn’t a TSMC issue at all.
AMD could "make" 10M chips a month and they would likely still be low on supplies. The global pandemic only caused a portion of the world to work from home. It wasn't everyone. As we move forward and until a vaccine is proven relatively safe and effective, expect shortages due to demand far outstripping production capabilities. Just ask Intel, who've been supply constrained for 3 years.

Others have already addressed this point, but if AMD really wants 5nm for hypothetical Warhol, they could probably get it done if their launch date is late H1 2021. It would certainly be easier for them to stick with N7+.
What does that leave for AMD then? Launch the tech stack and 5nm on Warhol without improvements in performance and bring performance in with Raphael? If you want to talk about constraints then Warhol will cause your constraint. No one knows what Apple's sales figures will be like as they launch more 5nm products. Their first Apple Silicon computers may very well be amazing and cause sales to double or triple. This is purely hypothetical. Apple's supply chain and JIT mantra that Tim Cook has nurtured over decades will help to a point. You may have had a point if GPUs would then come later, provided they were a monolithic die. Except most rumors point towards RDNA3 and NVIdia's hopper being chiplet. One is more expensive than the other to produce at scale due to die size and defects.

Matisse had them, and Summit Ridge also had them. With Matisse, it was mostly AGESA-related.
Matisse was BIOS issues. I'm not familiar with 1st gen Ryzen. Are you referring to segfaults that affected Ryzen mainstream or the mystery bugs that plague Ryzen TR 1st gen? How Windows addressed everything?


They are, but at the same time, we're kind of stuck. Micron and Hynix made significant advancements with e-die and CJR respectively, but Samsung isn't pushing A-die or M-die into the DiY market. Samsung b-die is still the cream of the crop when it comes to enthusiast performance, and it has been for a very long time. We should be seeing enthusiast A-die by now (in improved density no less) but we aren't. I suspect everyone is waiting for DDR5 to push performance memory products.
I'm not familiar with A-Die or M-Die. Though I don't go snorkling in memory chat like some such as yourself. Fact is, early DDR5 may be far too expensive to purchase except by those with deep pockets. DDR4 prices are beginning to slink downward. A 16 GB DDR5 set (assuming capacity can carry over and I'm not 100% well informed on it), you may see prices of $200-300 depending on demand and supply, and low speeds.

I just looked up DDR4 prices and am blown away. Just about 2 months ago a good set of DDR4 3200 16GB would set you back quite a bit. It's around $70 now. The good Crucial sticks dropped 30-60 bucks. :oops: Of course, knowing my damn luck they'll pop up back in price the day before I order my parts.

Core2 launched in 2006. 2005 was the critical period where AMD could have/should have responded by moving past K8. Ruiz infamously dismissed the threat, choosing instead to believe that Intel would stay with Netburst.
Typical design to product is around 3-5 years for a new processor design. If AMD would have responded, they would have had to begin in either 2002 or 2000. If they began in 2005 they wouldn't see their efforts for another few years up to 2010. If you want to give all the glory to Keller in this following example, then he joined AMD in 2012 and left in 2015. Ryzen was announced at the latter end, IIRC, and there was a demo at Hot Chips in 2016 on the Zen uarch. Ryzen hard launched in March 2017. I'll link to it just below this paragraph of text. Ruiz was and still is a moron. Though you're laying a bit of blame on him here. AMD reacting in 2005 would have already been late. Anyone paying attention to Intel would have known about Yonah and what it would bring. It was marketed in early 2005 and then launched the following year in January 2006. Ruiz's complacency and bad decisions drove AMD down.




Why not? The current management team isn't the same as in 2017, at least in terms of behavior. Same people, different actions. I think AMD is getting complacent. They might have much better reason to be so this time around - Intel is really struggling on the tech front. But I would rather they were a bit more paranoid ala Andy Grove. Also AMD really needs to continue punishing Intel with crushing benchmark wins in critical areas where Intel makes their money. Intel is making bank off bad tech. Rome hasn't moved the bar far enough. The sooner they can iterate through Milan to Genoa, the better. AMD has to chase that marketshare and mindshare. In the end, what we all need them to do is overtake Intel and then be a fundamentally better, more consumer-friendly company once they are sitting on top.

As a consumer, I don't think it's unreasonable to expect AMD to remain a technology-focused company that caters to the growing demands of users while making a healthy profit in the process.
That's strange wording. You'd be better off saying "AMD's management team behavior today is a stark contrast to that of 2017."

Semantics aside, why do you think AMD is being complacent? How does AMD benefit from being complacent when Intel is still a threat? Right now we estimate Intel won't be back onto their feet until say 2023-2025. That doesn't mean they might not have a breakthrough. AMD already crushes Intel in benchmarks and power use where Intel makes their money. They fall short on gaming due to core to core latency. CAD/CAM, Photoshop, Premier, etc. are software that prefer frequency due to not being heavily multithreaded. The iGPU for Intel QuickSync also helps when it comes to certain tasks like video rendering. It'll take a very, very, very, very, very long time for AMD to claw back their prior highs in the datacenter. Hardware cycles are longer nowadays and datacenters may still purchase Intel due to their setups and not wanting to validate AMD. Intel is practically giving away high core Xeons if Wendell is to be believed. Epyc is amazing, but it's also a new platform that has yet to prove itself year after year. Milan should establish even more street cred and Genoa should sell a lot. The next 2-3 years should see AMD increase their datacenter share by a factor of 2-2.5x. It really depends on how much power they can extract. Genoa may see a core count increase. I've had the number 96 suggested in a few industry calls. Not quite sure how they'd do that without increasing overall sizes unless layering come into the mix. Possibilities are "endless."

AMD overtaking Intel may take a decade. You'd really need to Intel to not only mess up in DC, but client and anything else they offer. They still have high revenue. Though with bean counters guiding the company, that day may come sooner. I'll put it in simple English.

If Zen 3's 4600X/5600X can give performance numbers of that of a really good 8 core, that's good. If it can do a theoretical 10 core Zen 2 processor or 12 core Zen 2 processor, that's amazing. Here's a simple breakdown of scores in popular mainstream benches to get a rough idea.


Ignore single core scores. It's likely the difference between single core scores will greatly increase than what's shown, and a mere 1.8-2x increase in multicore wouldn't be accurate as I believe Zen 3 will outstrip that.

Learn to read. I never said they would meet their demise. It's just that they are getting complacent, and soon that will lead to them being greedy. And if someone doesn't challenge them, they'll become the next Intel: rehash products, raise prices, squeeze consumers, etc. We need AMD to stay on a competitive footing at least so they'll keep their focus on continued advancements of technology irrespective of whether another company can seriously compete with them. That's what the semiconductor game has been about in the past, and that's what it should be about in the future until the laws of physics finally say "no". And we aren't there yet.
I can read. Learn to be real. If you think AMD is being complacent based on taking a few months longer while their cadence supports it and the XT lineup, then I can't help you. AMD is in zero position to be complacent. Their financials don't allow them to sit around and do little, especially with their competitor several times stronger than nearly 20 years ago. AMD doesn't have Intel's mind share. They probably won't for a long time. If you want to talk about greed, then releasing Warhol which offers zilch in performance a new tech stack in 2021 with Raphael around the corner for the same launch prices as Zen 3 is greed. Yay, AM5. Yay, new tech stack. Boo, no 5nm. Gotta buy Raphael for those sweet performance gains and 5nm! At increased prices again.

Yes, but TSMC has been known to produce multiple iterations of nodes at the same general feature size. For example:
Previously someone argued this was moot if they're made on the same lines. TSMC is confirmed to be expanding. Someone posted something online yesterday which stated TSMC were looking at building 2 or 3 fabs excluding one built in the center of Taiwan. Samsung's having issues with their nodes but they'll eventually figure it out... hopefully. I say that because it's healthier to have these two fabs compete with one another as it benefits end customers and companies we buy products from. TSMC was also looking into getting into the memory business a while back. I can see a world with TSMC, Micron (Crucial), Samsung and SK Hynix being the top 4 players in memory production.

That gives them N5 and N5P? At least? So Raphael could be N5P while Warhol could be N5.
If it's a new tech stack on top of a new node without significant performance gains, it needs to be priced half of what Vermeer launches at. A new tech stack and node do nothing for the consumer. No real USB4 products on the map. No PCIe5 drive development, just controllers. DDR5 expensive as heck. There is no real incentive. Unless AMD brings out Warhol with a 12-20% IPC increase over Vermeer, and Raphael brings 15-25% IPC increases over Warhol. Warhol would need to not regress on clock speeds from Vermeer, and Raphael would need to increase clock speeds over Warhol. Vermeer is rumored to have a 4.9 Ghz all core... excuse me while I go laugh my guts out.
 
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NostaSeronx

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Sep 18, 2011
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Or, Zen3 is 57CPP 5nm at TSMC and is cross-fab compatible with 5LPE at Samsung.

Then from above, Zen4 is 51CPP 5nm at TSMC and is cross-fab compatible with 3GAx at Samsung.

Vermeer (2021) => Raphael (2022)

N7+ => +10% perf and -15% power
N7+P/N5 => +5% perf and -15% power
N7+PP/N5P => +7% perf and -15% power

The truth revealed why N7 has Ps and N5 has Ps but N7+ has no P. It goes straight into N5.
 
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mikk

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May 15, 2012
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PC-Welt's "HMX3" to contain:
GPU: 2 x RTX 3090
CPU: R9 5900X

PC Welt on Zen 3: " we have no clue". AMD just promised them they will get the top SKU from Zen3, this is all they know. Boost speed, SKU naming, TDP is all based on Internet rumours, this is what they are saying. Absolutely useless if you are looking for Zen 3 infos in this video.
 

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