Speculation: Ryzen 4000 series/Zen 3

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Ajay

Diamond Member
Jan 8, 2001
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Personally I think an increase in the amount of cores won't happen with Zen 3 simply because that step will lack the density increase (TSMC's 7nm+ won't offer much there, the next big increase is for 5nm Zen 4 likely will use), lack the memory bandwidth (Zen 3 will still use DDR4, Zen 4 will use DDR5 requiring a new platform) and the current topology makes it tricky to add more cores without adding bottlenecks (currently with 64 cores each 8 core CCD is linked to one RAM channel, each pair of CCDs with one dual channel IMC on the IOD).

I believe Zen 3 will focus on internal changes in core and uncore that will then allow Zen 4 to massively scale out with a different package topology, similar to how it happened with Zen to Zen 2.
That would make Zen3 more like Zen2+, which AMD has said is not happening.
 

amrnuke

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Apr 24, 2019
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That would make Zen3 more like Zen2+, which AMD has said is not happening.
I guess the question is... why couldn't they just label minor changes as Zen 3?

We know Zen 2+ isn't happening but it's just a name.
 

lopri

Elite Member
Jul 27, 2002
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SMT has been on desktop for over a decade now, and Windows scheduler still have trouble making sense of it. Oh, and people now know that SMT is a security nightmare, due to inherent nature of resource-sharing design. If you want to share your bathroom with your guests, you'd better be sure you have no skeletons in the medicine chest.

I'd say SMT's time has passed now that core counts are actually increasing. Back in the day when the CPUs had one or two cores SMT made sort of sense, but today AMD and Intel's time will be better spent figuring out how many actual cores they can fit in a limited space without sacrificing performance/power.

AMD already tried to make a convoluted resource-sharing scheme work and failed miserably. It's called Bulldozer.
 

maddie

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Jul 18, 2010
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SMT has been on desktop for over a decade now, and Windows scheduler still have trouble making sense of it. Oh, and people now know that SMT is a security nightmare, due to inherent nature of resource-sharing design. If you want to share your bathroom with your guests, you'd better be sure you have no skeletons in the medicine chest.

I'd say SMT's time has passed now that core counts are actually increasing. Back in the day when the CPUs had one or two cores SMT made sort of sense, but today AMD and Intel's time will be better spent figuring out how many actual cores they can fit in a limited space without sacrificing performance/power.

AMD already tried to make a convoluted resource-sharing scheme work and failed miserably. It's called Bulldozer.
I disagree on the SMT statement. AMD has explicitly stated that computation/Joule will be the main limiting factor going forward. SMT is very useful in this performance parameter. Abandoning it is a regression in perf/W.
 

moinmoin

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Jun 1, 2017
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That would make Zen3 more like Zen2+, which AMD has said is not happening.
Not sure how you came to that conclusion after reading my text. I only wrote that I don't see any increase in cores (i.e. change in package topology like happened with Zen 2) coming for the aforementioned reasons, and that the changes will be in core and uncore. Zen+ (which you seem to take as reference) essentially had no changes at all aside process used and microcode (so software).

Even Papermaster stated late last year that the design focus for Zen 3 will be energy efficiency instead absolute performance.

SMT has been on desktop for over a decade now, and Windows scheduler still have trouble making sense of it.
It's the Windows scheduler.

Oh, and people now know that SMT is a security nightmare, due to inherent nature of resource-sharing design.
It's Intel's implementation of SMT. And this was essentially known since 2007 for whoever was listening to OpenBSD's Theo de Raadt who blasted Intel's MMU (memory management unit, the part that should prevent processes from accessing data they shouldn't be able to) even back then.
 
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NostaSeronx

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Sep 18, 2011
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Even Papermaster stated late last year that the design focus for Zen 3 will be energy efficiency instead absolute performance.
The same power efficiency as Excavator?

https://images.anandtech.com/doci/10436/Slide 9 - Power Frequency curve with libraries.png

Moving from 7.5T-HPC(DUV) to 6T-Mobile(EUV) would provide power efficiency. Zen2 (High Performance/Performance Optimized) -> Zen3 (Low Power/Power Optimized). AMD could also finally implement mixed-track; 6T(2-fin) for critical(lower dynamic leakage) and 5T(1-fin) for everything else(lower static leakage). Higher yields from EUV can mean higher overall frequency even with the track-height reduction.

The 256-bit FPU isn't cash money in power optimized workloads, I'm going to say Zen3 will probably go towards pure 4x 128-bit FMACs. With Zen4 bringing that back up to 256-bit FPUs. Leading to the two core conundrum which was leaked maybe?

zen2core.png

Remove the Hi-side of the FPU, plenty of room with a logic shrink to support another core(Control Unit(Instruction Retire Unit) + Datapath(Integer Execution)).
 
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Richie Rich

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Jul 28, 2019
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I guess the question is... why couldn't they just label minor changes as Zen 3?

We know Zen 2+ isn't happening but it's just a name.
AMD released "Software Optimization Guide for AMD Family 17h Models 30h and Greater Processors" .....it means there is no other architecture changes in 17h Family. Clearly Zen2 is last 17h Family CPU. So Zen3 is new 19h Family with some major changes. IMHO Zen2 is Zen1 upgraded by some new parts developed for Zen3 (FPU, L1 cache). Something like K6-III was.
 

DrMrLordX

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Apr 27, 2000
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2. I would be shocked to see SMT4 in Zen3. I really expect more cores are the most likely outcome (96?). I just don't see the need for more hardware threading at this point in Zen's development.
AMD may opt to widen the core (4-way to 6-way) without significantly changing their SMT implementation. It would be a viable strategy.

Power and Spark went with more hardware SMT to keep die size and power in check (relative to prior designs), rather than scaling core counts.
And they got clobbered doing so. Intel also went for SMT4 in Xeon Phi. Another dead product.
 

ChiefBigFeather

Junior Member
Jul 15, 2018
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Well, I think it is plausible Zen 3 will be more about improvements for the IO die then improvements in the core complexes. The process shrink is fairly modest, so I do not expect much room for architectural improvements on the cores. Maybe we are lucky and get some more L3, but I suspect it will be more like zen+: More frequency and some small timing improvements.

The IO die will probably see more of an upgrade this time around. It is new technology and probably has more low hanging fruits. We will almost definitely see some new power saving features, probably a die shrink too and some latency improvements here and there. This probably means fanless x670 (yay!).
The billion dollar question is whether we will see L4 cache. It seems to make sense as it addresses some (potential) bottlenecks for server architectures as well as SOCs. It generally seems the way forward if you believe the analysts. But I'm would suggest caution, as there may be lots of design and cost hurdles for this to overcome.
 

Richie Rich

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Jul 28, 2019
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Well, I think it is plausible Zen 3 will be more about improvements for the IO die then improvements in the core complexes. The process shrink is fairly modest, so I do not expect much room for architectural improvements on the cores. Maybe we are lucky and get some more L3, but I suspect it will be more like zen+: More frequency and some small timing improvements.

The IO die will probably see more of an upgrade this time around. It is new technology and probably has more low hanging fruits. We will almost definitely see some new power saving features, probably a die shrink too and some latency improvements here and there. This probably means fanless x670 (yay!).
The billion dollar question is whether we will see L4 cache. It seems to make sense as it addresses some (potential) bottlenecks for server architectures as well as SOCs. It generally seems the way forward if you believe the analysts. But I'm would suggest caution, as there may be lots of design and cost hurdles for this to overcome.
  1. We have evidence that Zen3 is new 19h Family CPU - this likely mean major core improvements. Zen2 was 17h Family CPU with its big IPC jump over Zen1. We can predict that 19h Family will bring something bigger - it might be Keller's big Zen developed from scratch since 2013.
  2. For Ryzen 4000 I can see no problem with pairing Zen3 chiplet + Zen2 IO die.
 

inf64

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Mar 11, 2011
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Zen3 to Zen2 is what Zen2 was to Zen1+. AMD hit the clock wall, you can expect major IPC uplifts from next 2 Zen iterations (in the range of Zen1->Zen2).
 

Richie Rich

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Jul 28, 2019
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Zen3 to Zen2 is what Zen2 was to Zen1+. AMD hit the clock wall, you can expect major IPC uplifts from next 2 Zen iterations (in the range of Zen1->Zen2).
Yes.
I would expect big +40% IPC change for Zen3 as being brand new architecture.
And smaller +10-20% IPC steps steps for Zen4 and Zen5 as being 19h Family improvements (cache latency, front-end optimizations etc.).
Zen5 might bring something new from next 20h Family... same way Zen2 brought Zen3 FPUs.

Timing is:
  • Zen3 2020 (19h Family) ... development started 2013/2014 ... now producing engineering samples..... new 6ALU core + SMT4 + doubling ZEN2 FPU (4x 256-bit FPU is ideal for SMT4)
  • Zen4 2021 (19h Family) ... development started 2018............. now under development .... brings 6nm and some optimalizations as Zen1+
  • Zen5 2022 (19h Family) ....development started 2019............. now started development and implementing Zen6 blocks.... brings 5nm + Zen6 FPU
  • Zen6 2023 (new 20h Family) ... development started 2016/2017 ... uarch concept is freezed, FPU blocks might be almost finished and ready for Zen5 adoption..... will bring 5nm new core 8xALU + SMT8 + doubling FPU units to support SMT8 performance.
So the real question is what is Zen6 because AMD engineers already know the main uarch parameters.
Who cares about Zen3? :D
 
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NostaSeronx

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Sep 18, 2011
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Do they have so many teams of engineers working at so many different architectures?
Yep.

Family 14h (Bobcat) => 40nm/28nm // Family 15h 00h-1Fh
Family 16h (Jaguar) => 28nm/16nm // Family 15h 30h-3Fh
Family 17h (Zen) => 14nm/7nm // Family 15h 60h-7Fh ++ the ARM versions of 17h. There is also Hygon's Family 18h(which has 2x SM4 vs 2x AES-128).
Family 19h (Zen3) => 7nm EUV/5nm EUV
Family 21h => 3nm High-NA EUV/2nm High-NA EUV

The Cat side has always been aggressive in architecture and nodes.
 
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Richie Rich

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Jul 28, 2019
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Do they have so many teams of engineers working at so many different architectures?
Its not about teams actually (project management). Its about pipeline (like stages in CPU), because you have different departments and CPU development must go through all of these stages:
  1. - concept&simulation department (probably working on post Zen6 (21h Family Zen9 uarchitecture) right now)
  2. - transistor logic blocs development department (core, front-end, IO, FPU teams) ... thats Zen5 +Zen6
  3. - silicon labs (Zen4)
  4. - production team - to create engineering samples and ramp up mass production (Zen3 and finishing APU Zen2)
So you can see that there are max two projects for the same department (one big/main and second is less risky smaller project).
And as a result there is a buffer of CPUs from Zen3 up to Zen9, so 5 CPU generations total currently under development. Im not counting small steps for Zen6 and Zen9, because Zen7, Zen8 only AMD stuff know how many small steps this uarch will need to improve, and Zen9 even AMD engineers doesn't know right know. So AMD can have 5 project teams who manage their product development. However there are more, console chips, APUs... IMHO. Just thinking loud.
 

Kocicak

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Jan 17, 2019
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  • Zen3 2020 (19h Family) ... development started 2013/2014 ... now producing engineering samples..... new 6ALU core + SMT4 + doubling ZEN2 FPU (4x 256-bit FPU is ideal for SMT4)
  • Zen4 2021 (19h Family) ... development started 2018............. now under development .... brings 6nm and some optimalizations as Zen1+
  • Zen5 2022 (19h Family) ....development started 2019............. now started development and implementing Zen6 blocks.... brings 5nm + Zen6 FPU
  • Zen6 2023 (new 20h Family) ... development started 2016/2017 ... uarch concept is freezed, FPU blocks might be almost finished and ready for Zen5 adoption..... will bring 5nm new core 8xALU + SMT8 + doubling FPU units to support SMT8 performance.
At what points are new sockets and memory implemented?
 

moinmoin

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Jun 1, 2017
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At what points are new sockets and memory implemented?
So far it seems Zen 4 at the earliest will be the time AMD will change platform to support DDR5.
It's confirmed that Milan (Zen 3 based Epyc 3) will still use the current platform.
 
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Ajay

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Jan 8, 2001
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Its not about teams actually (project management). Its about pipeline (like stages in CPU), because you have different departments and CPU development must go through all of these stages:
AFAIK, there are two main engineering teams working on Zen. That would be Zen3 and Zen4 right now. A fair number of members of the Zen3 team have likely already moved on to Zen5, and the rest will be following soon. Work on Zen6 won’t be starting till Zen4 is feature complete. I've never heard of a 'concept' group or a 'silicon lab' group, but feel free to elaborate. There are manufacturing, validation, test and other departments that likely run on ~1 year cycles making sure that final silicon gets out the door.

No doubt that Papermaster has a top level team overseeing Zen architecture (I forget the name of AMD's current lead architect). AMD is doing a lot with a relatively small engineering team - and that is probably Keller's most significant accomplishment when he was at AMD.
 

Tuna-Fish

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Mar 4, 2011
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So far it seems Zen 4 at the earliest will be the time AMD will change platform to support DDR5.
It's confirmed that Milan (Zen 3 based Epyc 3) will still use the current platform.
One of the big advantages of the chiplet architecture is that it would not cost AMD much at all to create the AM5 platform "early" and ship CPUs for both AM5 and AM4 sockets, using the same CPU chiplet but different IO chiplets. This is a substantial market advantage AMD now has compared to Intel, I would be genuinely surprised if they didn't make use of it.

(I also really want it to happen just because it would allow a near-perfect way of comparing DDR4 to DDR5 on almost identical platforms.)
 
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amd6502

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Apr 21, 2017
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One of the big advantages of the chiplet architecture is that it would not cost AMD much at all to create the AM5 platform "early" and ship CPUs for both AM5 and AM4 sockets, using the same CPU chiplet but different IO chiplets. This is a substantial market advantage AMD now has compared to Intel, I would be genuinely surprised if they didn't make use of it.

(I also really want it to happen just because it would allow a near-perfect way of comparing DDR4 to DDR5 on almost identical platforms.)
I could see Epyc next gen (NG) BGA socket and TR4 to TR5 jump pioneering DDR5 compatibility. For consumer/AM4 this won't make too much sense until DDR5 overtakes DDR4 in affordability. So for NG threatripper socket both graphics-out and DDR5 compatibility are on the wishlist. And as far as graphics this has been a long time coming, because quad channel and monster-iGPU are a natural fit.

And they can be co-produced with 7nm iGPU as you can tag along the optionally enabled IOX functionality onto a big GPU (over 30CU Vega-equivalent).
 
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soresu

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Dec 19, 2014
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No doubt that Papermaster has a top level team overseeing Zen architecture (I forget the name of AMD's current lead architect). AMD is doing a lot with a relatively small engineering team - and that is probably Keller's most significant accomplishment when he was at AMD.
I think the lead architect was Suzanne Plummer, but some of their staff went to work on RDNA/Navi I think - no idea if she is still running the shop at the moment.

Edit: seems she is still a top dog according to Linkedin

10599
 
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