Speculation: Ryzen 4000 series/Zen 3

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Ajay

Diamond Member
Jan 8, 2001
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Cross posted from the refresh thread; Zen 3 on 7nm. Thanks to @gdansk and TPU.

It looks like the refresh has not delayed Zen 3 desktop (or at least not much).

In the call, AMD told us that the information about "Zen 3" launching in 2020 is not under embargo, and so here we are. An AMD spokesperson told us that "the rumor on Zen 3 delay is inaccurate." AMD recently also refuted rumors of "Zen 3" being based on 5 nm, by putting out microarchitecture roadmap slides on the occasion of a recent investor relations event, which reaffirmed "Zen 3" as a 7 nm-class microarchitecture.
TPU
 

pike55

Junior Member
Jun 17, 2020
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If the 5nm rumors are wrong (still not sure ...) who else is taking up the capacity (5nm and other processes)?
We are talking serious business here:
Huawei is TSMC's second-largest client behind only Apple, accounting for 15% to 20% of the Taiwanese company's annual revenue. Huawei also accounted for up to 20% of SMIC's revenue, according to a Bernstein Research estimate.
Chip shipments bound for Huawei that went into production before May 15 and will ship before midnight Sept. 14 are not subject to the new rule, according to the document posted online by the U.S. Commerce Department's Bureau of Industry and Security. A license will be required for all other shipments.
 

jpiniero

Diamond Member
Oct 1, 2010
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Wouldn't surprise me if Digitimes just got confused about there only being 12 and 16 core available at launch.
 

Ajay

Diamond Member
Jan 8, 2001
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If the 5nm rumors are wrong (still not sure ...) who else is taking up the capacity (5nm and other processes)?
We are talking serious business here:

TSMC is still working with the US gov't to be able to manufacture HiSilicon SOCs. Also, AMD have booked a lot of 5nm capacity (for next year, IIRC) - so hopefully Zen 4 is coming b/4 the end of 2021. Apple is probably using a lot of wafers right now in preparation for iPhone 12.
 
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ksec

Senior member
Mar 5, 2010
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If the 5nm rumors are wrong (still not sure ...) who else is taking up the capacity (5nm and other processes)?
We are talking serious business here:

1. Those 5nm are LP node. Not for use on Desktop.
2. Huawei 5nm node order are fairly small, comparatively speaking. Highest 5nm node at launch will always be Apple.
3. The total capacity spared on 5nm will easily be eaten up by Qualcomm.
4. Huawei's order include lots of 7nm, dont worry about those. The market will eat them up for breakfast. ( Broadcom, Qualcomm, AMD etc... )

TSMC having over capacity is seriously a fabricated issue by media. You should worry more about not enough spare capacity. ( Which TSMC is on its course to further increase Capex )
 

DrMrLordX

Lifer
Apr 27, 2000
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Also, AMD have booked a lot of 5nm capacity (for next year, IIRC) - so hopefully Zen 4 is coming b/4 the end of 2021.
I hope you're right. That's supposed to be my next PC. I guess it's really going to be whatever is AMD's first 5nm desktop CPU, so if it's a Zen3 shrink then so be it.
 

LightningZ71

Senior member
Mar 10, 2017
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@Valantar , I've been scouring the web to find anything useful aside from that block diagram for the Renoir PCIe lane configuration. There's definitely a change from Picasso with respect to what's coming out of the die. Multiple motherboard vendor reference sheets are showing that Renoir APUs definitely show an x16 PEG link. There are a few, notably BioStar's, that show an odd configuration for their first 3 x16 (physical) slots, where it will support an x8/x8/x4 config with no caveats on M.2 port usage or other PCIe slot usage, whereas on Matisse, they show that same config having an issue with one of the PCIe x1 (physical) slots being occupied.

There is a note from VideoCardz that AMD included an additional x4 PCIe link, but I don't see any way that the AM4 socket allows an electrical connection to that additional slot. It may be coming from the chipset, but not properly indicated, but why would that change from Matisse to Renoir?

I'm beginning to think that the hard number of lanes on the die of Renoir is very differently expressed in the mobile package as compared to the desktop package, unlike Picasso and Raven Ridge, where there wasn't a whole lot of difference, save for the no connect on the chipset lanes. I agree that Renoir logically supports a pair of NVME PCIe connected storage devices. That's clearly indicated on the official block diagram and shown in actual shipping configurations. The question is, how do those signals get from the board to the die?
 
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Veradun

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Jul 29, 2016
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What is the chances when AMD does move to a new IOD die (Zen 4 I think), that they tap up Samsung 8nm for that?
Probably get a good deal, lots of capacity without affecting Tsmc supply, mature optimised process so performance and yields will be terrific.

What kind of performance benefits would that enable vs Global foundries 12nm?
I'm still betting on 12FDX
 

Valantar

Golden Member
Aug 26, 2014
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@Valantar , I've been scouring the web to find anything useful aside from that block diagram for the Renoir PCIe lane configuration. There's definitely a change from Picasso with respect to what's coming out of the die. Multiple motherboard vendor reference sheets are showing that Renoir APUs definitely show an x16 PEG link. There are a few, notably BioStar's, that show an odd configuration for their first 3 x16 (physical) slots, where it will support an x8/x8/x4 config with no caveats on M.2 port usage or other PCIe slot usage, whereas on Matisse, they show that same config having an issue with one of the PCIe x1 (physical) slots being occupied.

There is a note from VideoCardz that AMD included an additional x4 PCIe link, but I don't see any way that the AM4 socket allows an electrical connection to that additional slot. It may be coming from the chipset, but not properly indicated, but why would that change from Matisse to Renoir?

I'm beginning to think that the hard number of lanes on the die of Renoir is very differently expressed in the mobile package as compared to the desktop package, unlike Picasso and Raven Ridge, where there wasn't a whole lot of difference, save for the no connect on the chipset lanes. I agree that Renoir logically supports a pair of NVME PCIe connected storage devices. That's clearly indicated on the official block diagram and shown in actual shipping configurations. The question is, how do those signals get from the board to the die?
Yeah, I was thinking the same thing back when they first showed that block diagram, that AM4 has no way to connect more than x16 + x4 to the CPU no matter what you do. As such you're likely right that one of those x4 blocks is repurposed as a chipset uplink - after all, AMD chipset are just PCIe devices (AFAIK you could hook them up to any PCIe host if you had the ability - it sure would be interesting to see one desoldered, put onto an AIC and connected to an Intel CPU XD ). So you're probably also right that there's a bigger difference between mobile and desktop configurations this time around compared to previous APUs. If some boards support x8+x8 that must mean that the x16 controller supports bifurcation (the last x4 is undoubtedly from the chipset), which is excellent news (though it's still up to motherboard vendors to enable it).
 

Valantar

Golden Member
Aug 26, 2014
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Just want to note that AMD uses the LP/HD 7nm node for Zen 2 so that particular point is not working like you seem to think it is.
Isn't AMD supposedly going to use a somewhat custom 5nm node according to some rumors? Unlike 7nm it is at least conceivable for this to happen given AMD's massive growth recently (especially with upcoming datacenter growth). Not saying it's true, but there are definitely less plausible rumors out there.
 
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moinmoin

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Jun 1, 2017
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Isn't AMD supposedly going to use a somewhat custom 5nm node according to some rumors? Unlike 7nm it is at least conceivable for this to happen given AMD's massive growth recently (especially with upcoming datacenter growth). Not saying it's true, but there are definitely less plausible rumors out there.
DigiTimes reported that TSMC is doing a customized N5 for AMD, and that Apple now wants it too. But DigiTimes is also the source for the rumor that AMD would be using N5P this autumn already, so... ¯\_(ツ)_/¯
 

jamescox

Member
Nov 11, 2009
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I think you are mixing package technology and chip design approach. Having cache or memory as separate chips has been done for decades. HBM does that. With 386 cache was still external before it was moved into the chip with 486. And so on.

AMD so far only used MCM for packaging its chips, first only with Epyc/Threadripper for Zen/Zen+, now with both Epyc/Threadripper and desktop Ryzen for Zen 2. They talked about using other packaging technologies, interposer was considered for Zen 2 but MCM was more flexible (see slide 8 of 27).

In AMD's case “chiplets” specifically refers to the Zen 2 chips where the dies are no longer self sufficient (like Zeppelin was) but require a counterpart (CCD + IOD) to form a complete chip.


Indeed, which is why part of the discussion here was about how much of a lead time would be necessary for the rumor to be true.
I have been in the computer industry a long time. I am not mixing anything up. How would you define “self sufficient”? There is very little difference between an old style cpu that used a northbridge and a current Zen 2 cpu that essentially connects to an on package northbridge. In fact, the top level block diagram for AMD’s first dual socket Athlon looks exactly the same as current Ryzen 3000 processors, it is just on one package with Ryzen 3000. Dual socket Athlon used a system controller with memory controller, pci, etc. and two independent, point to point EV6 links to two Athlon CPU die. How is a Zen 2 chip much different from one of those Athlon CPUs?Both just have power/ground and a link to the chipset. AMD and intel have both made MCMs with multiple cpu cores. AMD had Magny-Cours which I believe was dual 6 core in one package. I believe we have had some MCMs with cpu and chipset previously also.

Anyway, this is semantics. As far as I am concerned, current Zen 2 parts are MCMs with chips. The term chiplet was initially used to refer to die made to go on a silicon interposer. They are fundamentally different since they use really wide links (1024 bit vs. 16 or 32 bit serdes and such). The wide links require huge numbers of pads and much smaller solder micoballs. You can’t take a chiplet and use it as a chip without a complete redesign normally. I guess you could put both interfaces, but that would be very wasteful and you may not have sufficient pad space on the die. The IFOP links on AMD processors are optimized for very short runs on package and they may use slightly different sized/spacing solder balls compared to just a BGA package meant to be soldered on a normal board, but they are probably a lot larger than silicon interposer microballs.
 

ksec

Senior member
Mar 5, 2010
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Just want to note that AMD uses the LP/HD 7nm node for Zen 2 so that particular point is not working like you seem to think it is.
I was referring to the 5nm node capacity left over from Huawei at "launch". Which is only LP node.

Unless AMD decide to use 5nm node on its Mobile APU at 5nm's launch ( i.e Expensive ) . Which I think ( I may be wrong, I thought we are talking about Zen 3 ) is not the issue we were discussing.

It is important to note this is launch capacity, which is the tight spot. There are not issues once you move past launch phases, market seems to have infinite appetite for wafers.
 

CHADBOGA

Platinum Member
Mar 31, 2009
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3900x + Radeon VII. I got that as an upgrade from 1800x + VegaFE. The goal was for Zen4 + maybe Big Navi (or 2nd gen Big Navi) in 2021, but at this rate, I'm not sure when Zen4 will be ready.
With a CPU that good already in your possession, why do you want to upgrade it so soon(relatively speaking)?
 

DrMrLordX

Lifer
Apr 27, 2000
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Right now I'm on a once-every-two-generations upgrade cycle, though if AMD starts dragging their feet I may have to rethink things.
 

mopardude87

Platinum Member
Oct 22, 2018
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Right now I'm on a once-every-two-generations upgrade cycle, though if AMD starts dragging their feet I may have to rethink things.
Same, i am hoping the bigger core chips in the 4000 series have a decent enough IPC and clock boost jump to justify the upgrade. Worst case its 5000 series for me and i just put all funds into my dual amperes a bit sooner. That is if this market relaxes a bit, i could just continue to save up and by the time it does relax i am golden on whatever. Good things come to those who wait. :)
 

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