Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[Kaluan]

Ur kidding me. The difference between a custom 4nm vs a custom 5nm node is way, way smaller than the samsung 10nm rebrand known as 8nm vs the tsmc 7nm used by AMD.
Also it might AIB models might clock higher, but how much extra perf are they getting from those clocks? Not much I'm guessing...

Oh boy, here come the useless hyperbole. Being 20% more dense and 10% less power hungry is a node rebrand these days.
Might as well say Cannon Lake and Raptor Lake use the same node at this point.

Truth is we have no clue what characteristics either of N31 or AD103 nodes have. So most of the conversation surrounding it is pointless. What we do know however is that AMD's is based on TSMC N5 or N5P and nVidia's is N4. I don't think TSMC would be OK with them mislabeling their nodes in public that much.

Anyway, 42% of N31's size isn't even part of that conversation. Or is TSMC N6 also the same as N4? lol

VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension

A look at Samsung’s 8nm 8LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

fuse.wikichip.org

 

[darkswordsman17]

It'll be interesting to see how much of the issues can be addressed in software updates. This release seems to be a condensed microcosm of all the issues AMD has had over like the past decade. Something going on with geometry culling (hello NGG on Vega), possibly some light screwup in voltage (if they're telling places to undervolt and adjust power profile or whatever had been an ongoing issue up to RDNA but reminds me of Polaris launch), and then built to clock higher but doesn't hit those clocks out the gate (GCN1).

We keep seeing how difficult modern GPUs are. Both companies put out big hot running expensive stuff this year. Hopefully the chiplet approach can be worked out and that can get us some better gains. I can't help but wonder if they're gonna need to take a different approach, like specialized processors instead of cramming so much (raster, geometry, rt, compute, etc) together I'm still personally underwhelmed with the hybrid ray-tracing and think I'd prefer playing more "game" looking stuff but with just higher raster/geometry performance coupled with lots of throughput to stream in textures/assets.

Granted, I'm barely even in this market any more. I wasn't likely to upgrade this year no matter what (would've taken something like the HD 5000 series where massive performance improvement paired with an Eyefinity like VR thing for me to even consider it). My next GPU buy will be when there's an affordable, quality 4K/120 VR headset that I can get my hands on easily. I'd say maybe next year but it might be another year or two unless the PSVR2 getting some good PC workaround. Which I'm still also disappointed we never got to see if per eye rendering for VR might have been a bridge for mGPU.

The display handling stuff (i.e. high power usage dual monitor, etc) makes me really wish they'd split that stuff off from the GPU as a completely separate chip, possibly coupled with video/image processing. And then include that on mobos and as dedicated cards, with the latter doing maybe input and streaming/handling of multiple feeds.

 

[Stuka87]

The display handling stuff (i.e. high power usage dual monitor, etc) makes me really wish they'd split that stuff off from the GPU as a completely separate chip, possibly coupled with video/image processing. And then include that on mobos and as dedicated cards, with the latter doing maybe input and streaming/handling of multiple feeds.

Funny enough, way back when AMD bought ATI, that was one of the things they wanted to do. They wanted to have a separate chip to handle all the 2d stuff that would socket into a slot on the motherboard.

Over time this changed into their idea of APUs. With the 7K series Ryzens having onboard graphics, it would be nice if they could switch between them easily. Kind of how laptops switch between the onboard graphics and the discrete graphics. But that system is far from perfect, as I still have issues with my Intel and nVidia chips playing nice in my Dell.

 

[gdansk]

conceptually isn't that met by the IGP in IOd of Ryzen now? it includes a tiny GPU because some desktop operation and even web pages now use 3d acceleration form time to time. by area the media transcoding and display interface make up most of the IGP.

but it can do the display output while your GPU does the rendering. in which case I don't think the shaders on the IGP are really used much

 

[maddie]

Several thousand dollars cheaper. N6 is cheaper because using EUV meant less machine time which meant TSMC could sell more wafers. A bit after it hit HVM, the price I heard was $4,000-$5,000 vs. $7,000-$8,000 for N7. That was from a reputable source. Prices have gone up for everything since then, but it is still much cheaper than N7 and N5.

Thanks for the reply, but I want another to answer. Too many definitive statements with no supporting info, all used to argue for higher prices across the board.

 

[eek2121]

AMD h

Thanks for the reply, but I want another to answer. Too many definitive statements with no supporting info, all used to argue for higher prices across the board.

Or maybe you just want to troll these forums. You will receive no official answer as TSMC only prices things under NDA, and like any responsible company, gives custom pricing based on volume.

I do get that you want factual evidence, however, with subject matter like this, you won't get it. Ian Cutress (formerly of AnandTech) released a piece regarding TSMC pricing. You should check it out. He is the closest thing to a source we have currently. Older information was leaked by a former TSMC employee that handled high volume orders (like AMD or Apple). Since that information has dried up, Ian is likely the next best thing.

I will counter and say "prove that N6 did not cost significantly less than N7".

You can't.

Respectfully,
Me.

 

[maddie]

AMD h


Or maybe you just want to troll these forums. You will receive no official answer as TSMC only prices things under NDA, and like any responsible company, gives custom pricing based on volume.

I do get that you want factual evidence, however, with subject matter like this, you won't get it. Ian Cutress (formerly of AnandTech) released a piece regarding TSMC pricing. You should check it out. He is the closest thing to a source we have currently. Older information was leaked by a former TSMC employee that handled high volume orders (like AMD or Apple). Since that information has dried up, Ian is likely the next best thing.

I will counter and say "prove that N6 did not cost significantly less than N7".

You can't.

Respectfully,
Me.

Is there a misunderstanding?

I'm originally asked for a cost because of this post.

N6 is not a cheap node. Cheaper than N5, definitely, but not cheap.

Edit: When AMD designed RDNA 3 several years ago, they probally thought N6 would be a cheap node by the time products launched. Which would be why they probally went with N6 rather than any alternatives.

This is done repeatedly and we also get prepped that prices will have to rise because of TSMC is raising already high prices. It was even claimed once that N6 is at best the same price as N7, the savings coming from the 10<>15% area scaling advantage.

 

[Joe NYC]

If it's a broken release it has to be rushed as well since it can't be planned as a broken release, nor was it delayed to polish it. So yeah, looks like a rushed release, 25 months after RDNA2 which points to the rumors of internal targets not being reached rather close to the launch to be at least partly right. And can't blame Raja for this one.

My theory / guess is that functioning of the graphics department of AMD broke down during Covid / remote work. And AMD did not put enough pressure to get people back into the office and working for real.

 

[Joe NYC]

It's not like the MCDs are free, esp being on N6.

They are not free, but N6 is a lot cheaper than N5, and AMD, likely being the biggest customer of N6/N7 probably gets the best price on N6 wafers.

 

[insertcarehere]

My theory / guess is that functioning of the graphics department of AMD broke down during Covid / remote work. And AMD did not put enough pressure to get people back into the office and working for real.

Countless companies have made boatloads of money and ran just fine while being fully/mostly remote over the last few years. Heck Zen 4 is a plenty fine product under the same conditions.

Excusing AMD's misteps here on remote work is weaksauce.

 

[Joe NYC]

Countless companies have made boatloads of money and ran just fine while being fully/mostly remote over the last few years. Heck Zen 4 is a plenty fine product under the same conditions.

Excusing AMD's misteps here on remote work is weaksauce.

Even if it is the most likely culprit?

A lot of posters seem to agree that released was "rushed". But perhaps the development timespan was just fine, but somewhere along the way, a lot of time / productivity was lost....

 

[maddie]

Countless companies have made boatloads of money and ran just fine while being fully/mostly remote over the last few years. Heck Zen 4 is a plenty fine product under the same conditions.

Excusing AMD's misteps here on remote work is weaksauce.

Not that I agree one way or the other, but, trying to reason why something happened and justifying why it happened are not the same thing.

 

[Mopetar]

At that point I'd have to wonder outloud to myself why the actual **** wouldn't AMD just lead with the N32 die and then launch the N31/7900XTX later when its sorted out?

Depends how late into production they discovered the issues. If they've already made a bunch of N31 dies, they're going to have to do something with them.

They might have needed to delay N32 in order to fix the problems there as well.

 

[Joe NYC]

Not that I agree one way or the other, but, trying to reason why something happened and justifying why it happened are not the same thing.

I think the complexity of RDNA 2 -> RDNA 3 was far greater than Zen 3 -> Zen 4.

In home renovation terms, Zen 4 is like adding extra pipe, changing wiring, building extra deck, setting up a room in the attic.

RDNA 3 is like setting dynamite on the old house, exploding it, and catching pieces as they come down, and arranging them in the entirely new fashion.

The complexity of this scale may be too much even in normal circumstances, never mind while being crippled by people working remotely. The best way to overcome problems is talking about them in formal or informal settings - such as lunch, in person.

Regarding "rushed" launch, my guess is that a deadline was set just to wake people up from the fantasy world of remote work being coddled like prima donnas, and get serious about delivering something.

 

[Mopetar]

I don't doubt that just moving to a MCM design added a lot of complications. Just because AMD has some experience with Zen doesn't mean that their GPU team knows all of the ins and outs or that there aren't any unique challenges to doing it for the first time.

AMD might have had an easier time with launching these products if they'd done some kind of RDNA2 refresh that used MCM just to iron out any of the kinks on that side of things.

 

[GodisanAtheist]

I do wonder what happened to the magical "pipe cleaner" product that we used to see back in the day. That low volume mid-range part that AMD and NV would use to dry run a new process or arch.

I wonder if AMD should have gone monolithic at the top end, MCM in the middle, then monolithic for the bottom again. People are a lot more forgiving of mid-range parts than they are of halo parts.

 

[Joe NYC]

I don't doubt that just moving to a MCM design added a lot of complications. Just because AMD has some experience with Zen doesn't mean that their GPU team knows all of the ins and outs or that there aren't any unique challenges to doing it for the first time.

AMD might have had an easier time with launching these products if they'd done some kind of RDNA2 refresh that used MCM just to iron out any of the kinks on that side of things.

It was a wholesale restructuring and re-optimization.

You may be right that it may have been smoother if they bit off a little less in each iteration and more frequent iterations.

But maybe RDNA was such a big restructuring that it had to be all at once, there wasn't any convenient middle step to go through.

 

[Geddagod]

It was a wholesale restructuring and re-optimization.

You may be right that it may have been smoother if they bit off a little less in each iteration and more frequent iterations.

But maybe RDNA was such a big restructuring that it had to be all at once, there wasn't any convenient middle step to go through.

I'm sure they could have tested the RDNA 3 architecture and its related clock speed bugs without going MCM yet, especially considering the non-chiplet models are rumored to have the same problems as well (meaning the clock speed bug isn't from chiplets but rather a problem in the architecture itself).

 

[Ajay]

I will counter and say "prove that N6 did not cost significantly less than N7".

N6 requires fewer masks, and thus few steps to manufacture a given chip. TSMC itself was trying to move customers to N6 since they could improve wafer output that way. So it's definitely less expensive. By how much, I do not know.

 

[Ajay]

My theory / guess is that functioning of the graphics department of AMD broke down during Covid / remote work. And AMD did not put enough pressure to get people back into the office and working for real.

You may be right. IIRC, AMD cut most of its driver team in the US and moved GPU driver development to China a few years ago (5??). Anyway, with all the hard lockdowns from the CCP's 'Zero Covid' policy - AMD's driver team may have been affected. Not sure how well the firmware team could accomplish remotely. There are better tools for remote work on physical hardware since I worked developing networking hardware firmware. Still, hard to imagine doing it all remotely if one had zero technicians at the lab to change configurations.

Still, who the heck knows.

 

[Mopetar]

I'm sure they could have tested the RDNA 3 architecture and its related clock speed bugs without going MCM yet, especially considering the non-chiplet models are rumored to have the same problems as well (meaning the clock speed bug isn't from chiplets but rather a problem in the architecture itself).

Navi 31 was always going to come first though so it's possible that they wouldn't have detected an issue until they had the full GPU assembled and MCM made this later than it would have using a traditional monolithic design. Using MCM may also have meant that resources were allocated to ensuring that worked out that may have otherwise caught the issue the chips have.

We may never know the real reason, but it seems like a plausible speculation as to that reason.

 

[JayMX]

Still talking about this mysterious 'issue' which no one knows what it is?
My guess is that the drivers are still in early beta, and that we will see significant improvements over time.

 

[gdansk]

Still talking about this mysterious 'issue' which no one knows what it is?
My guess is that the drivers are still in early beta, and that we will see significant improvements over time.

There is a list of hazards and bugs the open source drivers workaround (Kepler_L2 and Disenchantment have posted some snippets here). While it is possible AMD may find better workarounds it seems to be based on concrete hardware problems.

It may not be unusual to have extensive errata in consumer-focused GPUs but can have a big impact if it's in important features.

 

[Saylick]

There is a list of hazards and bugs the open source drivers workaround (Kepler_L2 and Disenchantment have been posted some snippets here). While it is possible AMD may find better workarounds it seems to be based on concrete hardware problems.

It may not be unusual to have extensive errata in consumer-focused GPUs but can have a big impact if it's in important features.

Yeah, the problem appears to be mostly a hardware issue, specifically the physical implementation of the architecture didn't quite pan out. Besides the abysmal V-F curve, what I've seen so far is that there's hardware issues related to the prefetchers, scalar ALU register file, and the OREO buffer, among other things. Drivers can mitigate the severity of these issues via workarounds, but workarounds almost always have performance penalties. At the end of the day, there's a compounding effect where both clocks and IPC suffered due to the hardware bugs.

 

[GodisanAtheist]

You may be right. IIRC, AMD cut most of its driver team in the US and moved GPU driver development to China a few years ago (5??). Anyway, with all the hard lockdowns from the CCP's 'Zero Covid' policy - AMD's driver team may have been affected. Not sure how well the firmware team could accomplish remotely. There are better tools for remote work on physical hardware since I worked developing networking hardware firmware. Still, hard to imagine doing it all remotely if one had zero technicians at the lab to change configurations.

Still, who the heck knows.

-The driver team has been releasing bangers more or less for RDNA 2 for essentially the entire pandemic, so not sure the remote work thing is specifically the issue...