Question Speculation: RDNA2 + CDNA Architectures thread

[uzzi38]

All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html

 

[Glo.]

Paul's info from RedGamingTech channel, regarding the RDNA2.

Best bit. According to his info there is 128 MB of Cache.

O_O

 

[Kenmitch]

Well according to the AMD news article
1. AMD doesn't seem to like the battle between AMD and NVIDIA that fans expect (what does that quote tell you?)
2. They don't want to be compared to Nvidia (why?)
3. AMD has its own timetable (makes sense)
4. Everyone is very interested in AMD 's new card, and they will try their best to share information that can be done (awesome)

Good news or bad news Kenmitch?

It was lost in the translation that somebody else clarified.

Well that is good. Seems like some mistranslation going on!

In the end that's how silly rumors get started.

 

[TESKATLIPOKA]

Paul's info from RedGamingTech channel, regarding the RDNA2.

Best bit. According to his info there is 128 MB of Cache.

O_O

I didn't bother to watch the video after reading this BS about 128MB cache. That amount of cache would be >=100mm2 which is totally unrealistic.

 

[Helis4life]

Paul's info from RedGamingTech channel, regarding the RDNA2.

Best bit. According to his info there is 128 MB of Cache.

O_O

Best bit because.... It's funny or because it might be true?

The sku breakdown doesn't inspire me with a lot of confidence tbh. 3080 to 3090 is maybe 20%. So if AMD had three skus in there, 6800, 6800xt and 6900xt there's not a lot of seperation between them.

Anyway I'm still of the opinion that no one right now knows anything at all and it's all guesses and assumptions

 

[maddie]

Paul's info from RedGamingTech channel, regarding the RDNA2.

Best bit. According to his info there is 128 MB of Cache.

O_O

This would explain to me the issue I have had with the rumored die size (505mm^2) and only 80 CU. I have previously said that either the die size is wrong (too big) or there are more than 80 CU. Cache taking the space of the missing CU would reconcile this.

 

[Stuka87]

Unless NV lied in their presentation, I don't see AMD releasing anything that is going to be enough of an improvement over the 3080 for me to regret buying one. Sure, they might come out with a card that beats it slightly in no DLSS/RTX/DXR performance, and uses maybe ~50w less power (who cares?), but if I know the 3080 meets my needs, and I can get one on launch day for ~$700, is it really worth waiting for AMD to maybe put out a a slightly better option and risking limited availability?

Even if there are no supply issues for both the NV (flawed 8nm process with low yeilds?) and AMD (large RDNA2 dies competing with higher margin Zen3?) GPUs, I suspect the demand is going to be huge as the previous generation of GPUs have been a massive let down (lots of ppl still on GPUS 2 or 3 gen old), the holiday season approaches, tons of people are going to be building new rigs when Zen3 is released, and Cyberpunk is coming out.

If the reviews of the 3080 check out, and AMD still hasn't said anything to make me confident that RDNA2 is both worth waiting for and will be available before mid-November, I'll be trying to get a 3080 on Thursday.

nVidia was very sneaky with how they posted their performance. Everything was relative, with no actual numbers. Marketing people should pretty much never be trusted. We will find out Monday.

Why do you think every rumor about RDNA2 is wrong? And why do you think AMD RT implementation is going to be bad?

RDNA is not competing with Ryzen for wafers, they are on a different process (Different versions of 7nm), and AMD has purchased all the wafers they will need (They are the #1 customer for 7nm at TSMC).

If waiting an extra month is that hard, then sure, get the nVidia card. But if I was spending $700+ on a GPU, waiting a month seems like a worth while thing to do.

 

[Glo.]

Paul also said that AMD achieved more than 50% performance per watt uplift, in the range of 60%.

Best bit because.... It's funny or because it might be true?

The sku breakdown doesn't inspire me with a lot of confidence tbh. 3080 to 3090 is maybe 20%. So if AMD had three skus in there, 6800, 6800xt and 6900xt there's not a lot of seperation between them.

Anyway I'm still of the opinion that no one right now knows anything at all and it's all guesses and assumptions

Best bit because its totaly ludacris.

128 MB of cache, in theory could allow you for TERABYTES of internal bandwidth. It also could explain, as Maddie mentioned, why the die is so big with just 80 CUs...

Just imagine pulling this feat of engineering. 128 MB of cache, over 2 GHz clock speeds, 275W TGP, and 80 CUs in just 500 mm2 die.

That is purely mind blowing physical design enginnering.

 

[Helis4life]

Paul also said that AMD achieved more than 50% performance per watt uplift, in the range of 60%.

Best bit because its totaly ludacris.

128 MB of cache, in theory could allow you for TERABYTES of internal bandwidth. It also could explain, as Maddie mentioned, why the die is so big with just 80 CUs...

Just imagine pulling this feat of engineering. 128 MB of cache, over 2 GHz clock speeds, 275W TGP, and 80 CUs in just 500 mm2 die.

That is purely mind blowing physical design enginnering.

How would it alleviate the lack of memory bandwidth though? And is that much cache a good engineering choice vs having a 512 bus some such?

 

[rainy]

Just imagine pulling this feat of engineering. 128 MB of cache, over 2 GHz clock speeds, 275W TGP, and 80 CUs in just 500 mm2 die.

What about memory bus, could be 256-bit or rather wider?

 

[Glo.]

What about memory bus, could be 256-bit or rather wider?

I guess, we will see.

 

[Saylick]

How much area does A100's 40 MB of L2 cache take up, because 128 MB of cache ( assuming it's L2 and not total cache) would be a huge amount of area.

Edit: Okay, just realized we don't have that info as no die shots are released. Is the only source of information we have to guesstimate how much area such a cache would take up be using Zen 2's cache as reference? Do we have a Navi 10 die shot?

 

[Olikan]

Welp, RDNA2 have 16 slices of L2... if true, each slice went from 256kb to 8MB....

 

[DiogoDX]

128mb of cache reminds me of the RT coprocessor rumor.

 

[Helis4life]

It all sounds a bit wishy washy. Is only the too SKU getting such a massive cache, does the Xbox and ps5 use something similar, if not why not

 

[Helis4life]

128mb of cache reminds me of the RT coprocessor rumor.

Maybe the same "source" is responsible for both

 

[DiogoDX]

It all sounds a bit wishy washy. Is only the too SKU getting such a massive cache, does the Xbox and ps5 use something similar, if not why not

XboX SX has 5mb of L2 cache buy Microsoft in the hotchips presentation. Navi 10 has 4mb.

 

[Saylick]

Xbox Series X is only 5 MB L2.

 

[Saylick]

Is it possible that the 128 MB cache is off-die?

 

[Olikan]

Edit: Okay, just realized we don't have that info as no die shots are released. Is the only source of information we have to guesstimate how much area such a cache would take up be using Zen 2's cache as reference? Do we have a Navi 10 die shot?

IIRC, pretty much 1mm per 1MB

 

[Saylick]

IIRC, pretty much 1mm per 1MB

You're right. I realized the same when I remembered the L3 cache in Zen 2 takes up half the CCD (70 something mm2) at 32 MB, so about 1mm2 per MB.

 

[Tup3x]

Best bit. According to his info there is 128 MB of Cache.

O_O

Not going to happen.

 

[Gideon]

Is it possible that the 128 MB cache is off-die?

An interesting idea, but I don't think it would make any sense.

• You can't really put it on top of the chip due to heat issues
• If you're going to put it on package you'll need an interposer:
  • Intel had 128MB of eDRAM in it's old Broadwell products (called Crystal Well) but these only had 100 GB/s bandwidth which is at least an order of magnitude too little.
  • If you already have an interposer anyway, it would be pretty dumb to not just use HBM2 as your memory.
• And finally, if this were the case, it would have to be called L3 not L2 as there already is on-chip L2 on RDNA2 (xbox slides). There is no way an off-chip cache would have comparable bandwidth or latency

 

[Gideon]

Not going to happen.

Yeah, I also don't have much faith in that rumor.

I hope they have more than 8MB (that is what a 80CU RDNA1 chip would have), but 128MB seems ... odd and unnecessary.

 

[CastleBravo]

An interesting idea, but I don't think it would make any sense.

• You can't really put it on top of the chip due to heat issues
• If you're going to put it on package you'll need an interposer:
  • Intel had 128MB of eDRAM in it's old Broadwell products (called Crystal Well) but these only had 100 GB/s bandwidth which is at least an order of magnitude too little.
  • If you already have an interposer anyway, it would be pretty dumb to not just use HBM2 as your memory.
• And finally, if this were the case, it would have to be called L3 not L2 as there already is on-chip L2 on RDNA2 (xbox slides). There is no way an off-chip cache would have comparable bandwidth or latency

Would a 128 MB on-die eDRAM L3 cache make any sense?

 

[sontin]

No, it doesnt. Microsoft scraped the idea with the Xbox One X.