It happens to the best of us. However this data should be taken with a bit of grain of salt. The figures are a little low for both TSMC and Intel, but shouldn't be far off. For example TSMC nanjing fab (16nm process) started volume ramp to a capacity of 25,000 wpm in 2020, which is not reflected in the table. Intel's actual fab capacity is kind of mysterious, partly because they gradually update their fab to newer node, unlike foundries. And different sources give quite different data for Intel's capacity.
Intel showed prodigious 14nm capacity at many fabs. The 14nm wpm numbers were significantly higher than TSMCs throughput on modern nodes. Intel's 10nm numbers were, of course, much lower. However, if my sources were wrong (and I don't even remember where I looked them up anymore), then its useless information anyway.
That seems a bit low for Intel. 135k wpm for 2020 vs 340k wpm for TSMC. Obviously not all of those (or even anywhere near that many) go to AMD, but the financials make me question it a little bit. Intel's 2020 (not sure if that lines up perfectly with the actual calendar year) revenue was reported as about $78 billion. TSMC was $48 billion for 2020. Granted Intel also sells the chips they make, but if you look at AMD's 2020 financials they only made about $10 billion in revenue. Nvidia made about $11 billion and although they swapped over to Samsung for their Ampere cards, they still likely did a lot of business with TSMC as well.
Granted we can't just do something quite so quick and dirty as addd the revenues for TSMC, AMD, and Nvidia together to make a comparison, but Intel seems like they're making a lot more money than they should be if they're only got 135k WPM, and a lot of that is on older nodes that aren't going to be useful for new products soon.
Granted we can't just do something quite so quick and dirty as addd the revenues for TSMC, AMD, and Nvidia together to make a comparison, but Intel seems like they're making a lot more money than they should be if they're only got 135k WPM, and a lot of that is on older nodes that aren't going to be useful for new products soon.
I guess another way to verify / guestimate the figures is to try and take die sizes, expected yields and see how many chips that would give Intel?
I make it that TSMC have about 1,000,000 7nm (normal, "plain") wafers per year (90,000 * 12 = 1,080,000).
Since I'm still trying to get an idea of (all) the causes of the GPU shortage, my question is, how much are Sony and Microsoft using of that?
8+ million consoles using 308mm2 (Sony) or 360mm2 (MS) per console is a lot of wafers.
I make it that TSMC have about 1,000,000 7nm (normal, "plain") wafers per year (90,000 * 12 = 1,080,000).
Since I'm still trying to get an idea of (all) the causes of the GPU shortage, my question is, how much are Sony and Microsoft using of that?
8+ million consoles using 308mm2 (Sony) or 360mm2 (MS) per console is a lot of wafers.
I remember reading something that either Sony alone or both Sony and Microsoft together accounted for 30k wafers per month during the past year.
I never bothered trying to do any math to see how well it lines up. We also don't know exactly when they started or if that use ramped up and if so what the ramp looked like. You can probably work backwards from the die size to figure the total wafers used based on sales though.
I never bothered trying to do any math to see how well it lines up. We also don't know exactly when they started or if that use ramped up and if so what the ramp looked like. You can probably work backwards from the die size to figure the total wafers used based on sales though.
Try Intel's revenue versus TSMC and all of their customers revenue combined. Fab to final end user revenue train.
That gets too messy since not all of their customers fab everything at TSMC. Many of them also add a further layer to their revenue because they don't sell the chips, but rather use them to build some product that they sell. If I wanted to go that route should I add the revenue that Dell makes from selling computers with Intel CPUs?
It's also messy because some of those customers don't have the position of AMD, Intel, or Nvidia who largely dominate their markets as a duopoly and don't have as much pressure on the prices they charge. Many of TSMCs customers are selling components in competitive markets that greatly lowers their revenues.
I just used those as a bit of quick napkin math. The revenue breakdowns that have been posted for TSMC also show that they earn a lot of revenue from older nodes that wouldn't be included in the figures above, so you'd have to subtract that portion out as well.
So is the conclusion that foundry business isn't as lucrative as selling end products? Remember that Intel was in little trouble couple years ago when they signed to produce modems for Iphones with their 14nm process, that deal take not insignificant part from their production which affected availability of their own products - at the same time TSMC did produce SOC for every IPhone and other phone manufacturers.....
Ajay
Lifer
- Jan 8, 2001
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Google tells me that 10 million PS5 and 6 million Series X have been sold as of June. Based on those die sizes, that's in the ballpark of 60k wafers total - or about two weeks of TSMC's yearly N7 capacity.
If AMD is contracting that production directly, then bigger than expected sales of consoles means fewer wafers for AMD's own products.
That's not how yields are calculated.
You've taken the area of a 300 mm wafer (about 70,000 mm²) and divided it by the die size:
But a yield calculator will take into account the shape, scribe lines, defect rate and so on:
CALY Technologies
caly-technologies.com
which is about 12% of TSMC's annual output.
Now what we don't know is
- the actual defect density. I put down 0.09 per cm².
- In Microsoft's case, what the split of Xbox Series X and Xbox Series S is.
- What the truth is about Sony's PS5 chip having bad yields (or more precise binning as they are unable to hit the speed they want - the PS5's clocks were meant to have been pushed higher sometime before launch).
Certainly AMD have been very supply constrained: high Zen3 prices, Zen3 APUs still not launched for retail, no ThreadRipper, RDNA2 cards even less available than Nvidia's despite this gen mining a lot worse, etc.
EDIT: fixed the layout of the second image being inline
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I should have gone to a die size calculator - I did it in my head adjusting for M1 and messed up the math!
However, I doubt it is anything like 120K wafers total, because AMD would have included some redundancy in there - and TSMC's N7 is pretty mature now so I can't believe they'd be getting yields as poor as 73%.
Even if it is 120K that's still only a month's worth of output. I imagine that a shrink to N6 will be forthcoming soon.
However, I doubt it is anything like 120K wafers total, because AMD would have included some redundancy in there - and TSMC's N7 is pretty mature now so I can't believe they'd be getting yields as poor as 73%.
Even if it is 120K that's still only a month's worth of output. I imagine that a shrink to N6 will be forthcoming soon.
Well it is very tricky to deduce wafer number just from revenue. But Intel enjoys very high margin for their chips. As for TSMC's fabless customers, a very low fraction of actual chip sales contributes to TSMC's revenue (for example Nvidia has a gross margin of more than 60%, which means only 30+% of chip sales pay for the manufacturing of the chip, and this manufacturing cost includes not only wafer cost(which goes to TSMC/Samsung), but also chip testing, packaging etc). So TSMC makes quite a lot more wafers than Intel and ends up with less revenue.
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Console chips are designed to be more defect tolerant, because console chips are low margin business, so AMD cannot afford to just throw away chips with defects. These chips are designed with redundancy, For example, Xbox Series X chips actually have 56CU, but only 52CU are enabled.That's not how yields are calculated.
You've taken the area of a 300 mm wafer (about 70,000 mm²) and divided it by the die size:
But a yield calculator will take into account the shape, scribe lines, defect rate and so on:
Which yields totally different figures:CALY Technologies
which is about 12% of TSMC's annual output.
Now what we don't know is
But 12% is not bad figure. I rather suspect it is more than that mainly due to PS5 yields which I think cannot offset the Xbox Series S being smaller.
- the actual defect density. I put down 0.09 per cm².
- In Microsoft's case, what the split of Xbox Series X and Xbox Series S is.
- What the truth is about Sony's PS5 chip having bad yields (or more precise binning as they are unable to hit the speed they want - the PS5's clocks were meant to have been pushed higher sometime before launch).
Certainly AMD have been very supply constrained: high Zen3 prices, Zen3 APUs still not launched for retail, no ThreadRipper, RDNA2 cards even less available than Nvidia's despite this gen mining a lot worse, etc.
a
So your guess are in the ball park, but I suspect real yield should be a little higher than your calculation.
That said, the real yield we probably will never know, there are so many variables at play.
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I agree with you, it's a bit low for Intel.
I'm gonna do an analysis of Intel's logic fab capacity based on currently available information when I'm free. Feel free to check it then.
Really depends on the product. If it's something like an iPhone that has a lot of other value added on top of just the SoC, or a professional chip like those that go into Nvidia's Tesla (I think they're just calling them Data Center GPUs now) GPU accelerators where one card sells for as much as the entire wafer it was cut from then no it isn't. If you're selling components that twenty other companies are also manufacturing then you're probably making less money than the fab is.
The defect density used in the calculations was from some information that TSMC made publicly available over a year ago so it's probably gotten a little bit better as the process has matured. However, defect density is a function of die size so if you have lager dies and an average number of defects that will occur on a given wafer then you'd expect more dies to have a defect of some sort. Smaller dies or chiplets distribute that same number of expected defects over a larger number of dies which is why the yield rate will be above 90%.
Of course just because there's a defect doesn't mean that the chip is useless. Both consoles already disable some of the hardware so that they have an easier time ensuring that most chips can be used because even if something isn't defective, it might not be able to hit the required clock speeds across all cores or be able to do so within the required power constraints. If the defect is in some area of the chip that could be disabled artificially for those reasons then it doesn't matter because that core can just be one of the ones that gets shut off. The console chips are dominated by their GPUs which are also the most redundant parts of the chip. So of the 40 supposed defective dies, something like 20 probably just have a defective shader that can be turned off and otherwise work fine.
moinmoin
Diamond Member
- Jun 1, 2017
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It has to, since production of x86 IP is not transferable.
Of course, the wafers for consoles are of particually interest to see how many Zen3 CCDs they could have made.
120,000 wafers would make a lot of Zen3 CCDs. The yield calculator has Zen3 CCDs as about 650 good dies per wafer so that's about 78,000,000 Zen3 CCDs. Obviously IO dies, packaking etc would have to be added to that where there might be next to impossible shortages.
Still, for the question how much marketshare could AMD supply that would a huge share.
Zen3 margins would have to suffer to shift that many parts, but they should be far better than console margins or GPU margins.
120,000 wafers would make a lot of Zen3 CCDs. The yield calculator has Zen3 CCDs as about 650 good dies per wafer so that's about 78,000,000 Zen3 CCDs. Obviously IO dies, packaking etc would have to be added to that where there might be next to impossible shortages.
Still, for the question how much marketshare could AMD supply that would a huge share.
Zen3 margins would have to suffer to shift that many parts, but they should be far better than console margins or GPU margins.
- Oct 22, 2004
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Intel's upcoming IDM 2.0 webcast should be interesting:
"Intel is accelerating its annual cadence of innovation with new advancements in semiconductor process and packaging under its IDM 2.0 strategy announced in March. Join a webcast with CEO Pat Gelsinger and Dr. Ann Kelleher, Senior Vice President and General Manager of Technology Development, where they will provide a deeper look at Intel’s process and packaging roadmaps."
www.intel.com
"Intel is accelerating its annual cadence of innovation with new advancements in semiconductor process and packaging under its IDM 2.0 strategy announced in March. Join a webcast with CEO Pat Gelsinger and Dr. Ann Kelleher, Senior Vice President and General Manager of Technology Development, where they will provide a deeper look at Intel’s process and packaging roadmaps."
- When: 2 p.m. PDT, Monday, July 26.
- Event Replay: A video replay will be available on the Intel Newsroom following the webcast.
Intel Accelerated
Intel CEO Pat Gelsinger and guests provide an update on Intel's IDM 2.0 strategy.
www.intel.com
- Oct 22, 2004
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Interestingly, AMD's gross margins are currently lower than TSMC's. Intel's have traditionally been higher but have been falling rapidly lately and are now at the same level as TSMC's.
AMD Profit Margin 2006-2021 | AMD | MacroTrends
Taiwan Semiconductor Manufacturing Profit Margin 2006-2021 | TSM | MacroTrends
Intel Profit Margin 2006-2021 | INTC | MacroTrends
I was surprised when I recently learned that TSMC now achieves more than 50% gross margin. In my thinking about Intel's fabless future, I've always assumed that they wouldn't be interested in running a foundry as a substantial part of their business, since I presumed it would drag down their overall margins considerably. However, due to competition in the x86 and server space their gross margins on their products are coming down anyway. So, perhaps Pat Gelsinger sees an inevitable future where Intel will have to give up historically high gross margins at 60% and above and learn to live comfortably around 50% instead.
So, my thinking has evolved somewhat. I still think that Intel design and manufacture will transition to an industry-standard fabless model, with much more flexibility when it comes to where chips are made (ex-CEO Bob Swan and new CEO Pat Gelsinger have both explicitly stated this now), while Intel Foundry Services (IFS) will gradually subsume all of Intel's manufacturing operations under independent management and accounting (IDM 2.0 with unfair priority and service for Intel designs is unsustainable). The question now is whether Intel keeps IFS as a fully owned subsidiary, akin to Samsung Foundry, does a joint venture with part ownership, sells it (with a minority stake, maybe), or even tries to IPO it as a separate business.
But first Pat Gelsinger will have to build up IFS into a viable foundry competitor on the global stage. I think Intel will try to acquire the necessary capabilities for IFS to succeed (ref. GlobalFoundries takeover). If they cannot acquire the capability, I think a joint venture is in the cards.
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- Oct 22, 2004
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I liked the presentation a lot. Good to have more clarity on Intel's process and product schedule going forward. This should help dispel unrealistic expectations for quick turnaround and product delivery out of the blue.
The webcast communicates a new focus on roadmap execution very much in Lisa Su's style, while they adopt much of TSMC's modus operandi, from process naming to yearly incremental cadence.
Strangely, despite being an AMD investor with no fondness for Intel products and marketing, I wish IFS success. I hope they are able to execute well and can become a viable competitor to TSMC and Samsung, as to rebalance the semiconductor supply chain around the world. But independence is a must, so I will watch closely how IFS develops in that regard.
Here is AnandTech's report on the webcast, including nice roadmap graphics:
https://www.anandtech.com/show/16823/intel-accelerated-offen...
The webcast communicates a new focus on roadmap execution very much in Lisa Su's style, while they adopt much of TSMC's modus operandi, from process naming to yearly incremental cadence.
Strangely, despite being an AMD investor with no fondness for Intel products and marketing, I wish IFS success. I hope they are able to execute well and can become a viable competitor to TSMC and Samsung, as to rebalance the semiconductor supply chain around the world. But independence is a must, so I will watch closely how IFS develops in that regard.
Here is AnandTech's report on the webcast, including nice roadmap graphics:
https://www.anandtech.com/show/16823/intel-accelerated-offen...
- Oct 22, 2004
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At timestamp 1:20:21, in a long discussion with PC World, Dr. Ian Cutress, Senior Editor here at AnandTech, talks about the organisational issue for Intel Foundry Services (IFS), and his view (which I share, and which I have expressed in this discussion thread) that "it only works" if Intel makes it a separate business unit with Intel product division as a customer. Separate management and accounting is key, I think, and is already underway, as I understand it. It will be interesting to see what further organisational steps Intel takes to ensure its independence.
Panino Manino
Senior member
- Jan 28, 2017
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From maybe going fabless to fabbing for everyone.
I hope, I just hope, that Intel will not get too strong.
I hope, I just hope, that Intel will not get too strong.
They may still go fabless. If they can create a viable foundry business, they might spin it off and become its largest customer, like AMD did with GF.
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