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[SemiAccurate] Intel kills off the 10nm process

Mar 10, 2006
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My prediction is that Icelake Client is based upon a modified version of the 14 nm SoC process they call 10 nm; and maybe they will throw in the FPGAs on it. But that's it for 19 and 20.
Why?
 

jpiniero

Diamond Member
Oct 1, 2010
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Because they can't fix the original 10 nm and they reassigned all the production lines to 14 nm.

There was a rumor that one of the last ideas BK had was a special project that Murthy was tasked in executing; what I described is what I think it is. And it's not like it doesn't mean that Icelake mobile won't be a nice improvement over Whiskey Lake.
 
Mar 10, 2006
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Because they can't fix the original 10 nm and they reassigned all the production lines to 14 nm.

There was a rumor that one of the last ideas BK had was a special project that Murthy was tasked in executing; what I described is what I think it is. And it's not like it doesn't mean that Icelake mobile won't be a nice improvement over Whiskey Lake.
Murthy just confirmed that they didn't change the density specifications of 10nm at the Dec. 4 Nasdaq investor conference.

https://edge.media-server.com/m6/p/sxqkw2g8
 

coercitiv

Platinum Member
Jan 24, 2014
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Murthy just confirmed that they didn't change the density specifications of 10nm at the Dec. 4 Nasdaq investor conference.
So does this mean Charlie's accurate leak streak is finally at an end? :)
 

jpiniero

Diamond Member
Oct 1, 2010
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Murthy just confirmed that they didn't change the density specifications of 10nm at the Dec. 4 Nasdaq investor conference.

https://edge.media-server.com/m6/p/sxqkw2g8
That makes me pretty "nervous" that they have nothing and know it. Figure the absolute best case would have been to cut the density 10% so they can reduce or eliminate the 4+ pattern layers or wait long enough so that EUV would become viable.

They could certainly do another low volume release like Cannonlake for Icelake Client and just call it high volume.
 
Mar 10, 2004
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Or they have the problems solved and don't need to change the density?
 

maddie

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Jul 18, 2010
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That makes me pretty "nervous" that they have nothing and know it. Figure the absolute best case would have been to cut the density 10% so they can reduce or eliminate the 4+ pattern layers or wait long enough so that EUV would become viable.

They could certainly do another low volume release like Cannonlake for Icelake Client and just call it high volume.
They can introduce a 12nm and still say 10nm is unchanged. How to keep the investors contented (ignorant?) for as long as possible might be the game. They need to ride out a rough few years by any means possible.
 
Mar 10, 2006
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They can introduce a 12nm and still say 10nm is unchanged. How to keep the investors contented (ignorant?) for as long as possible might be the game. They need to ride out a rough few years by any means possible.
They did introduce a "12nm" -- it's called 14nm+/14nm++.
 
Mar 10, 2006
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So does this mean Charlie's accurate leak streak is finally at an end? :)
The full quotes from Murthy:

The ambitions for 10 haven’t changed. I mean even though we have had the trials and tribulations with 10, the power and performance and transistor density targets that we set in 2014 remain the same.
We could have taken two approaches, we could have slackened off on the tech specs of 10 nanometers and move towards a faster schedule or we could have maintain the tech specs and basically done the work to get it out on the timeline we talked about. And that’s really because of the resiliency that we have been able to engineer in 14 nanometers.
Intel doesn’t really do a great job in terms of speaking about its manufacturing technology, I think, in that scenario we can become sharper on. But we have had three iterations of 14 nanometers within the last few years. I mean if you look at the performance of the current generation of 14 nanometers shipping products compared to the very first generation from a process-only perspective we have improved that 30% to 40%, so the transistor improvement. I mean that’s kind of like the more so then half in many respects. So, yeah, I think, one thing we should be clear is that we have had multiple iterations of 10 -- 14 nanometers…
 

moinmoin

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Jun 1, 2017
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"Targets" being the keyword I guess. Whether/when they reach them and for what products they actually use them being a different story.
 

Vattila

Senior member
Oct 22, 2004
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the power and performance and transistor density targets that we set in 2014 remain the same
I think the key here is that the performance targets are the same. Remember that performance targets for 10nm, as well as the planned incremental improvement 10nm+, were well behind 14nm++ (and probably more so by now). Not until 10nm++ would performance be competitive. Back in March 2017, at Intel's Technology and Manufacturing Day, 10nm++ was projected to be ready sometime in 2019 (see slide below). That was before further delays, and before the latest rumours about the process not being viable. So I am doubtful that 10nm++ will materialise in that timeframe. I guess 10nm may be relegated to a subset of products that gain from the power and density, while 14nm will continue to be used for the high-performance products.

I suspect (some) 10nm conversion plans have been cancelled (hence SemiAccurate's cancellation claim). This concurs with Intel's announcement this year of $1B investment into expanding 14nm capacity (source), which I understand means converting fabs/tools from planned 10nm production to expanding 14nm production. Meanwhile, I guess Intel will focus on keeping their 7nm Arizona Fab 42 on schedule. It was announced back in February 2017 that it would be ready in 3-4 years, which means 2020-2021 at the earliest.

Note that their 7nm process depends on EUV readiness.

9114301_21d739c5693d263e8f253dd46c3aab6c.png


https://s21.q4cdn.com/600692695/fil...ufacturingDay/2017_TMD_KaizadMistry_FINAL.pdf
https://newsroom.intel.com/news/intel-presents-technology-manufacturing-day-live-video-updates/
 

jpiniero

Diamond Member
Oct 1, 2010
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The issue has always been the defect rates caused by using QP+ in so many layers, plus perhaps the cobalt. So it's not a performance issue per se, but rumors were that the yields were in the single digit percentage even at the point of the 8121U's 'launch'.

Like how I think it was supposed to go was the 8121U would be released by a model with the GPU (partially) enabled a couple months later but since they couldn't get the yields to go anywhere they released the 8130U.
 

Spartak

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Jul 4, 2015
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By just relaxing the M2 pitch from 36 to 40nm they should in theory be able to move to double patterning instead of quad for the M1 and M2 pitch. This would likely have no consequence for overal transistor density. And like jpiniero said, replacing cobalt for copper might also solve their issues without impact on density and their performance targets. Either or both could be enough to solve their issues.
 

itsmydamnation

Golden Member
Feb 6, 2011
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The issue has always been the defect rates caused by using QP+ in so many layers, plus perhaps the cobalt. So it's not a performance issue per se, but rumors were that the yields were in the single digit percentage even at the point of the 8121U's 'launch'.

.
Dave Kanter thinks contact over gate is a big problem for them as well.
 

jpiniero

Diamond Member
Oct 1, 2010
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By just relaxing the M2 pitch from 36 to 40nm they should in theory be able to move to double patterning instead of quad for the M1 and M2 pitch. This would likely have no consequence for overal transistor density. And like jpiniero said, replacing cobalt for copper might also solve their issues without impact on density and their performance targets. Either or both could be enough to solve their issues.
I would think there would be some amount of density loss doing that. That was the 10% I was talking about. Not a big deal in the scheme of things but tangible.
 

Spartak

Senior member
Jul 4, 2015
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The M2 is only one from about 12 metal pitches IIRC, so Im not sure it has a measurable impact on the transistor size. But transistor density relates to the spacing of these transistors, besides their size, so overal density would probably or possibly not be affected.
 

jpiniero

Diamond Member
Oct 1, 2010
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NTMBK

Diamond Member
Nov 14, 2011
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https://videocardz.com/79267/intel-ghost-canyon-x-nuc-to-feature-8-core-16-thread-core-i9-9xxxh-cpu

NUC roadmap leak until the end of 2020. Nothing using Icelake is in there; only Comet and Whiskey and Coffee Lake Refresh. They could always add an Icelake model but doesn't seem like Icelake will be that high of volume.
PCIe x16 slot? At what point does "NUC" stop being a NUC, and start just being a regular mini-ITX system? 0_o Weird that Intel is happy to start encroaching on traditional system-builder territory.
 

NostaSeronx

Platinum Member
Sep 18, 2011
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https://www.anandtech.com/show/13683/intel-euvenabled-7nm-process-tech-is-on-track
Post in relationship to the above:

193i vs NZ2C vs NZ3C
https://i.imgur.com/0ayX1Sl.png <== 1st
https://i.imgur.com/Ev6LQZP.png <== 2nd

Older 2016: https://i.imgur.com/aGaiyjE.png

I really don't get the EUV hype train, when there is the JFIL hype train.

NAND / DRAM / CPV / LED / Logic / Misc/etc
No natural monopoly... EV Group could get their heads out of the ground, the many other smaller NIL groups can go HVM for specific markets.
 
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Mar 10, 2006
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PCIe x16 slot? At what point does "NUC" stop being a NUC, and start just being a regular mini-ITX system? 0_o Weird that Intel is happy to start encroaching on traditional system-builder territory.
What's going on with mini-STX these days? I like that form factor.
 

NTMBK

Diamond Member
Nov 14, 2011
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mikk

Platinum Member
May 15, 2012
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Murthy Renduchintala did also confirm 7nm is on track, a different team is working on it.

7 nm for us is a separate team and largely a separate effort. We are quite pleased with our progress on 7 nm. In fact, very pleased with our progress on 7 nm. I think that we have taken a lot of lessons out of the 10 nm experience as we defined that and defined a different optimization point between transistor density, power and performance and schedule predictability. […] So, we are very, very focused on getting 7 nm out according to our original internal plans.”
https://www.anandtech.com/show/13683/intel-euvenabled-7nm-process-tech-is-on-track
 

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