With respect to the upcoming 1600 , 1500 and 1400 ryze models.
What got me wondering, with a ccx being a quad core and having 8 MB L3 cache, that cache is partitioned to at least 2MB for each core. Otherwise, hypothetically one core would use up all the L3 and the others would have none and the L2 tags needs storage as well. It got me wondering that when AMD has a 2 + 2 configuration or 3 + 3, the usable size of L3 for each core must increase as well. For only 2 cores per ccx, that seems easy.
4MB for each core. But with 3 cores for each ccx, 2 2/3. Which is not a binary number. I wonder how the cache is setup in these cases. Would it be rounded off to the first binary number ?
I mean, hypothetically a flexible format where one core could use all of L3 (with exception of storage for L2 tags for the other cores) when other cores need none, (An ideal situation that would never happen) and then suddenly other cores need the L3 victim cache as well, then there would need to be a policy of what is still left in the L3. I assume after L1 , L2 is checked and then L3, If not present, go to dram. That would cause weird timings in threads that run.