Ryzen: Strictly technical

Discussion in 'CPUs and Overclocking' started by The Stilt, Mar 2, 2017.

  1. looncraz

    looncraz Senior member

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    This is because you are using high performance mode. Don't do that. You need core parking enabled to park those logical cores when they do more harm than good.
     
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  2. looncraz

    looncraz Senior member

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    Ryzen (and Excavator before it) will "stretch" the clock to even out power demand over short intervals to improve power usage and stability on lower core voltage at higher clocks. The only way you'll see this is by some jitters in the base clock as the multiplier doesn't change - the stretch can be as much as 7%, but only lasts about a millisecond (it basically reacts to instantaneous Vdroop).

    AMD now calls this "Pure Power," now, I think.
     
  3. plopke

    plopke Member

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    For all we know microsoft did not change anything except update some drivers , i vaguely remember amd stating the windows ryzen driver would be updated like a month or so after release.
     
  4. Ajay

    Ajay Diamond Member

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    Since power management is SMT aware, maybe MS will do something there that helps there. At this point I'm kinda done with the lack of knowledge about vis-a-vis details of Ryzen's cache/DF/memory subsystems. I'll wait till the next stepping of Zeppelin shows up and take a look again (hopefully there will be some tweaks to the IMC and a few other features).
     
  5. Ajay

    Ajay Diamond Member

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    Like an ACPI device driver?

    Edit: duh.
     
    #1080 Ajay, Mar 20, 2017
    Last edited: Mar 21, 2017
  6. innociv

    innociv Member

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  7. bjt2

    bjt2 Senior member

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    I have an old laptop with celeron dual core and intel 4 series chipset, and this update cut in less than half the time to recover from hybernation. No other enhancement on my old system, but still noticeable...
     
  8. JimmiG

    JimmiG Platinum Member

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  9. iBoMbY

    iBoMbY Member

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    Why would anyone want to enable core parking? Core Parking is known to cause all kinds of problems, and has almost no benefit at all.
     
  10. R0H1T

    R0H1T Platinum Member

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    Core parking works if/when you want to save power, it's mostly useless otherwise, even for Intel processors. The fact that something like a process lasso does a better job at handling core parking & unparking, not to mention setting affinities or even I/O & memory priority, than Windows itself is testament to the shellacking Microsoft's done to their OS. The Android governors on the other hand are much better at handling multiple cores, thanks in part due to big little, remember how octa cores were ridiculed on phones & yet Windows is the one that can't handle 8 cores properly.
     
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  11. sm625

    sm625 Diamond Member

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  12. Doom2pro

    Doom2pro Senior member

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    ROFL more like a service pack!
     
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  13. LTC8K6

    LTC8K6 Lifer

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  14. JimmiG

    JimmiG Platinum Member

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    Core parking also helps with XFR, so if you're not overclocking, there's that.
     
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  15. Dresdenboy

    Dresdenboy Golden Member

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    Have to answer again. Somehow you look familar, BTW. ;)

    iBoMbY made the aforementioned list.
    It's not exactly, what one gets in GB/s by calculating mem clock [GHz] * 32 because of a GB being 1.074 billion bytes, but it gives a good impression.
     
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  16. TerionX6

    TerionX6 Junior Member

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    Zen/Zeppelin seem obviously geared towards absolute power savings. The decision to tightly couple the IMCs and uncore was a move for efficiency of data transfer, and this appears to corroborate with Zen's considerably higher actual vs. theoretical sustained transfer compared to Intel's products. I think that just about every piece of that silicon was designed with a goal of meeting or exceeding the power characteristics, with few exceptions, Intel is currently capable of while still on an inferior node. This has created a chip with great potential in deployments scaling from a workstation to massive clusters, great potential going forward.
    Zen is AMD's Core2/Nehalem in a sense.

    My assumptions:
    The GMI/IMC (and coupled PCIe/BCLK strap) is clearly the major limiting factor for this design for home users. Zen2 will again not "win" in the home/gamer market unless AMD had planned on significantly revamping the chips clock domains.
    Zen2 certainly won't be on 14LPU (at first), much too late in the design phase. No easy 10% clock improvement there.
    2x inter-CCX > 1x IMC speeds may be a pipe dream for Zen F4 stepping, but man would that solve a heck of a lot of latency issues (while skyrocketing uncore power draw)

    The Stilt, have you gotten your hands on any other 1800x samples to compare Vmin/Fmax? Would be interesting to see possible ranges of binning for a single SKU.
     
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  17. SpaceBeer

    SpaceBeer Senior member

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    What about Raven Ridge CPUs (APUs)? They will have only one CCX (+ up to 11 GPU CUs). So there will be no "issues" with CCX communication

    So those SKUs with less GPU CUs might be better choice for gaming?
     
  18. looncraz

    looncraz Senior member

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    Core parking is absolutely vital for Windows scheduling with SMT. Windows' scheduler is likely completely unaware of SMT or much of anything else. Everything is done with external processes/daemons simply creating and sorting lists which the scheduler uses.

    Core parking will preferentially park logical cores - giving the scheduler the appearance of being SMT aware.
    Without it, you'll never see dual core turbo clocks or XFR on Ryzen and you'll see logical cores being used as if they're real cores.

    This is why some people are seeing a sudden improvement in a few cases with the new Windows update - core parking was re-enabled and they didn't notice.
     
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  19. innociv

    innociv Member

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    Windows scheduler seems perfectly aware of Ryzen's SMT.

    It's applications doing their own scheduling that aren't.
     
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  20. looncraz

    looncraz Senior member

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    Applications can't do their own scheduling (with the exception of those rare kernel-on-kernel designs), they spawn threads and apportion their workload amongst those threads. Some apps are simply spawning too many worker threads and seeing negative scaling as a result because they assume AMD has no SMT and treat it like it has 16 cores.

    Some apps may use thread affinity to prevent threads from roaming around, but most don't bother.
     
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  21. rvborgh

    rvborgh Member

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    i wonder how many games use User Mode Scheduling.

    https://msdn.microsoft.com/en-us/library/windows/desktop/dd627187(v=vs.85).aspx
     
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  22. looncraz

    looncraz Senior member

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    I always forget about UMS. Not sure how commonly it would be used by games - considering how poorly most scale with core, I'd imagine not that often (since the investment in implementing its use would not be worthwhile unless you are using a task-base processing model).
     
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  23. beginner99

    beginner99 Diamond Member

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    And it seems to be 64-bit only. I never really bothered to check but how many games actually are 64-bit only nowadays? Ok, probably most but it is a rather new development. Are the game engines pure 64-bit? Don't know.
     
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  24. Kromaatikse

    Kromaatikse Member

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    I know of at least one game which is definitely 64-bit only.

    By contrast, The Talos Principle has 32-bit and 64-bit binaries included.
     
  25. imported_jjj

    imported_jjj Senior member

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    Wouldn't it be fun if AMD had their ARM version of Zen on existing sockets? In both consumer and server.
    Would be so much easier to sell ARM, especially in consumer and maybe they could even get Microsoft on board.
    TSMC N7 HPC should be ready for tapeouts in June 2017 so a nice 8-12 ARM cores for AM4 next year could be quite interesting.

    They wouldn't sell much in consumer but it's important to have ARM as a deskstop platform, otherwise ARM in server remains an uphill battle.
    Using the existing infrastructure (sockets) would reduce costs for both AMD and customers.
    Ofc it would be a substantial financial effort, unless they already need the ARM core on TSMC's N7 HPC for semi-custom.