Discussion RISC V Latest Developments Discussion [No Politics]

[DisEnchantment]

Some background on my experience with RISC V...
Five years ago, we were developing a CI/CD pipeline for arm64 SoC in some cloud and we add tests to execute the binaries in there as well.
We actually used some real HW instances using an ARM server chip of that era, unfortunately the vendor quickly dumped us, exited the market and leaving us with some amount of frustration.
We shifted work to Qemu which turns out to be as good as the actual chips themselves, but the emulation is buggy and slow and in the end we end up with qemu-user-static docker images which work quite well for us. We were running arm64 ubuntu cloud images of the time before moving on to docker multi arch qemu images.

Lately, we were approached by many vendors now with upcoming RISC-V chips and out of curiosity I revisited the topic above.
To my pleasant surprise, running RISC-V Qemu is smooth as butter. Emulation is fast, and images from Debian, Ubuntu, Fedora are available out of the box.
I was running ubuntu cloud images problem free. Granted it was headless but I guess with the likes of Imagination Tech offering up their IP for integration, it is only a matter of time.

What is even more interesting is that Yocto/Open Embedded already have a meta layer for RISC-V and apparently T Head already got the kernel packages and manifest for Android 10 working with RISC-V.
Very very impressive for a CPU in such a short span of time. What's more, I see active LLVM, GCC and Kernel development happening.

From latest conferences I saw this slide, I can't help but think that it looks like they are eating somebody's lunch starting from MCUs and moving to Application Processors.


And based on many developments around the world, this trend seems to be accelerating greatly.
Many high profile national and multi national (e.g. EU's EPI ) projects with RISC V are popping up left and right.
Intel is now a premium member of the consortium, with the likes of Google, Alibaba, Huawei etc..
NVDA and soon AMD seems to be doing RISC-V in their GPUs. Xilinx, Infineon, Siemens, Microchip, ST, AD, Renesas etc., already having products in the pipe or already launched.
It will be a matter of time before all these companies start replacing their proprietary Arch with something from RISC V. Tools support, compiler, debugger, OS etc., are taken care by the community.
Interesting as well is that there are lots of performant implementation of RISC V in github as well, XuanTie C910 from T Head/Alibaba, SWerV from WD, and many more.
Embedded Industry already replaced a ton of traditional MCUs with RISC V ones. AI tailored CPUs from Tenstorrent's Jim Keller also seems to be in the spotlight.

Most importantly a bunch of specs got ratified end of last year, mainly accelerated by developments around the world. Interesting times.

 

[camel-cdr]

I would've shared some slides from RISC-V Summit China, but the forum won't let me, so I'll just share some info's from the RISC-V Summit China. I only managed to catch a few of the talks via live-stream, so I don't have the full picture.

Canonical has access to RVA23 hardware through FPGAs and have a demo of the XuanTie C930 running Ubuntu on display. This may explain the early pivot to RVA23, it means Canonical can effectively validate and importantly performance optimize for RVA23.
This also confirmed that the C930 has VLEN=256 configurations and it looks like they target a frequency of >3.4GHz.

NVIDIA is actively porting CUDA drivers to RVA23, although it was noted that this is still early days.

There were some interesting slides comparing XiangShan Kunminghu V2 and Nanhu V5 area to other chips: on 7nm: KunmingHuV2 (before -> after optimizations): 2.65 -> 1.73 mm^2, 2.4W -> 1.63W; Neoverse N2: 1.7 mm^2, 1.5W

Here is a list of planned XiangShan Kunminghu V3 targets/upgrades mentioned in the slides: 22 SPEC2006/GHz, 2.3 SPEC2016/GHz, 3.0-3.2GHz, 2.5-3mm^2, 1.5-2W, on 7nm-5nm, 8-wide decode, 2-take branch prediction/fetch (yes, I think this is like the thing Zen5 introduced), full RVA23 support, new fusion cases, and other general upgrades.

I've listed the planned RVV implementation changes separately (machine translated from a slide):

• Complex vector instructions now use dedicated functional units instead of complex decode and split
  • New gather unit offers 16x throughput, 1/8 latency
  • Removed temporary logic registers to expand the vector scheduling window
• Optimized vector uop splitting
  • Reduced the maximum number of uop splits
  • Reduced non-vector resource usage
• Added speculative wake-up between uops
  • Back-to-back wake-up for non-predicate uops
• Optimized continuous memory access vector instructions
• Optimized vector decoding
  • Reduced first-level vector decode pipeline stages

The Tenstorrent slides had barely any different information that earlier ones, but they slightly bumped the excepted Acalon SPEC scores: SPEC2016 from 18/GHz -> 20/GHz (Ascalon+/Ascalon++ where also bumped), Athena (8-core Ascalon) SPEC2017: 35 -> 36

 

[Io Magnesso]

I would've shared some slides from RISC-V Summit China, but the forum won't let me, so I'll just share some info's from the RISC-V Summit China. I only managed to catch a few of the talks via live-stream, so I don't have the full picture.

Canonical has access to RVA23 hardware through FPGAs and have a demo of the XuanTie C930 running Ubuntu on display. This may explain the early pivot to RVA23, it means Canonical can effectively validate and importantly performance optimize for RVA23.
This also confirmed that the C930 has VLEN=256 configurations and it looks like they target a frequency of >3.4GHz.

NVIDIA is actively porting CUDA drivers to RVA23, although it was noted that this is still early days.

There were some interesting slides comparing XiangShan Kunminghu V2 and Nanhu V5 area to other chips: on 7nm: KunmingHuV2 (before -> after optimizations): 2.65 -> 1.73 mm^2, 2.4W -> 1.63W; Neoverse N2: 1.7 mm^2, 1.5W

Here is a list of planned XiangShan Kunminghu V3 targets/upgrades mentioned in the slides: 22 SPEC2006/GHz, 2.3 SPEC2016/GHz, 3.0-3.2GHz, 2.5-3mm^2, 1.5-2W, on 7nm-5nm, 8-wide decode, 2-take branch prediction/fetch (yes, I think this is like the thing Zen5 introduced), full RVA23 support, new fusion cases, and other general upgrades.

I've listed the planned RVV implementation changes separately (machine translated from a slide):

• Complex vector instructions now use dedicated functional units instead of complex decode and split
  • New gather unit offers 16x throughput, 1/8 latency
  • Removed temporary logic registers to expand the vector scheduling window
• Optimized vector uop splitting
  • Reduced the maximum number of uop splits
  • Reduced non-vector resource usage
• Added speculative wake-up between uops
  • Back-to-back wake-up for non-predicate uops
• Optimized continuous memory access vector instructions
• Optimized vector decoding
  • Reduced first-level vector decode pipeline stages

The Tenstorrent slides had barely any different information that earlier ones, but they slightly bumped the excepted Acalon SPEC scores: SPEC2016 from 18/GHz -> 20/GHz (Ascalon+/Ascalon++ where also bumped), Athena (8-core Ascalon) SPEC2017: 35 -> 36

this is interesting

 

[marees]

NVIDIA is actively porting CUDA drivers to RVA23, although it was noted that this is still early days.

At the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA) on the CPU side of things. The news was confirmed during a presentation during a RISC-V event.

Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm

Yet another alternative.

www.tomshardware.com

https://twitter.com/x/status/1946251939823370697

 

[DZero]

So... nVIDIA is testing the waters of RISC-V? That could be HELLA interesting.

 

[igor_kavinski]

So... nVIDIA is testing the waters of RISC-V? That could be HELLA interesting.

Only way they can get a "free" CPU of their own without paying anyone any royalties.

I would not be surprised if they pay a billion or two for Ahead Computing...

 

[DZero]

Only way they can get a "free" CPU of their own without paying anyone any royalties.

I would not be surprised if they pay a billion or two for Ahead Computing...

Remember my post of the crazy idea of Nintendo trying to go RISC-V?
With that, it won't be as far fetched after all.

 

[DrMrLordX]

All it means is that NV will have a software stack ready in case someone makes a RISC-V-based host system. It doesn't necessarily mean that NV will be giving up on Grace et al anytime soon.

 

[DZero]

All it means is that NV will have a software stack ready in case someone makes a RISC-V-based host system. It doesn't necessarily mean that NV will be giving up on Grace et al anytime soon.

Of course not, Grace is their Opus Magnus for ARM, but I don't be surprised if it cost a lot and wants cheaper options in the meantime.

 

[LightningZ71]

Remember, very large businesses also employ leverage. Continuing to invest small sums into RISC-V to keep it closer than fusion (always closer than fusion) helps to keep ARM's licensing costs in check.

 

[DZero]

Remember, very large businesses also employ leverage. Continuing to invest small sums into RISC-V to keep it closer than fusion (always closer than fusion) helps to keep ARM's licensing costs in check.

But also allows to have an escape way in cases ARM goes wild.

 

[igor_kavinski]

Why can't some of these billionaires just pool their money and make the latest ARM design open-source (let's call it OpenARM) and ARM is free to design a newer one. Then it will be a race between ARM and the rest of the world advancing OpenARM instead of RISC-V's fragmentation and immaturity.

 

[poke01]

Why can't some of these billionaires just pool their money and make the latest ARM design open-source (let's call it OpenARM) and ARM is free to design a newer one. Then it will be a race between ARM and the rest of the world advancing OpenARM instead of RISC-V's fragmentation and immaturity.

Why can’t Intel and AMD open source x86 designs? Same reason

 

[Mopetar]

So... nVIDIA is testing the waters of RISC-V? That could be HELLA interesting.

They've been a big sponsor of RiSC-V for years and years. It's not surprising that they'd offer official support for it like this.

 

[igor_kavinski]

Why can’t Intel and AMD open source x86 designs? Same reason

They both have a vested interest in keeping it closed source. But billionaires like to show off their philanthropic activities. Instead of trying to end world hunger (which they never can because to teach to fish is never having to donate a fish again but they don't teach fishing), they should prop up ARM so market competition can really heat up, creating millions of jobs and accelerating innovation faster than it's happening right now.

 

[Doug S]

They both have a vested interest in keeping it closed source. But billionaires like to show off their philanthropic activities. Instead of trying to end world hunger (which they never can because to teach to fish is never having to donate a fish again but they don't teach fishing), they should prop up ARM so market competition can really heat up, creating millions of jobs and accelerating innovation faster than it's happening right now.

You're not getting it. They can't legally do this, and it doesn't matter how much money they have. Apple for instance has an architectural license that lets them design their own cores. They can't "open source" their designs though even if they wanted to, because ARM owns the ISA and Apple merely holds a license to it that allows them to use it only in ways the license specifies. And it does not specify "create a design and open source it for others to use".

That's like asking why someone doesn't "open source" their copy of the Windows ISO, or a put a scan of their Harry Potter books on their website for anyone to read.

 

[Io Magnesso]

Why can't some of these billionaires just pool their money and make the latest ARM design open-source (let's call it OpenARM) and ARM is free to design a newer one. Then it will be a race between ARM and the rest of the world advancing OpenARM instead of RISC-V's fragmentation and immaturity.

In the first place, ISA open source and architecture open source have different meanings

 

[igor_kavinski]

You're not getting it.

I was suggesting that the billionaires band together to give ARM a sweet deal where the investors get enough money so that they let the latest ISA/architecture be open-sourced. We have what? Over a 1000 billionaires in the world? Let's suppose only 100 of them each donated $5 to $10 billion towards this cause. Would ARM investors say no to something like half a trillion $$$ of essentially "free" money for doing nothing other than opensourcing their "current" trade secrets and then carry on and develop new trade secrets to stay in the business?

 

[poke01]

Wouldn’t it best for these hypothetical billionaires to invest in RISC-V? Make sure this ecosystem grows

 

[igor_kavinski]

Make sure this ecosystem grows

RISC-V ecosystem can't agree on anything. Ask @Nothingness

With ARM v9.4 or whatever the latest ISA version is, they can hit the ground running.

Server space can go do SMT4 or SMT8.

Console space can do ARMX3D with huge cache.

Someone could come up with the ultimate Transmeta Crusoe clone built with ARM ISA that emulates x86-64 and the CPU warms up to full speed in 24 hours.

Another team could pay homage to P4 with 10 GHz speeds.

Etc. Etc.

 

[Io Magnesso]

ARM v9.4 has not yet been released

 

[Io Magnesso]

And ARM still has a lot of microarchitectures in the mainstream ISA.
but ARM is by no means the latest ISA
It's not as long as x86, but ARM has a long history

I was suggesting that the billionaires band together to give ARM a sweet deal where the investors get enough money so that they let the latest ISA/architecture be open-sourced. We have what? Over a 1000 billionaires in the world? Let's suppose only 100 of them each donated $5 to $10 billion towards this cause. Would ARM investors say no to something like half a trillion $$$ of essentially "free" money for doing nothing other than opensourcing their "current" trade secrets and then carry on and develop new trade secrets to stay in the business?

 

[Doug S]

I was suggesting that the billionaires band together to give ARM a sweet deal where the investors get enough money so that they let the latest ISA/architecture be open-sourced. We have what? Over a 1000 billionaires in the world? Let's suppose only 100 of them each donated $5 to $10 billion towards this cause. Would ARM investors say no to something like half a trillion $$$ of essentially "free" money for doing nothing other than opensourcing their "current" trade secrets and then carry on and develop new trade secrets to stay in the business?

Let's say 1000 billionaires got together and agreed to invest a half trillion however you say in order to do something you think would make the world better? Buying ARM and open sourcing it is your one big idea? I sure am glad you aren't in charge of any charitable foundations!

Even if the remit was limited to CPU design you don't think a half trillion dollars could go a long way for RISC-V? Why would it need the "head start" ARM has in the face that incomprehensible sum of money? Or do a new clean sheet ISA? Or perhaps best of all, given that it is a half trillion, invest in creating a whole family of new clean sheet ISAs, each with different targets? For example, maybe you do a "safe" RISC ISA, an aggressive RISC that tries out a bunch of unproven ideas, a VLIW (that includes lessons learned from Itanium) and to put a cherry on top perhaps something way way out there like Mill. Fund them all, give them access to the best designers, the best processes. May the best ISA win!

 

[Doug S]

ARM v9.4 has not yet been released

Not AFAIK in any currently shipping chips, but ARM has already released specs for v9.6 last year. We'll see v9.7 this fall.

https://developer.arm.com/documenta...scriptions/The-Armv9-6-architecture-extension

 

[igor_kavinski]

Even if the remit was limited to CPU design you don't think a half trillion dollars could go a long way for RISC-V? Why would it need the "head start" ARM has in the face that incomprehensible sum of money? Or do a new clean sheet ISA? Or perhaps best of all, given that it is a half trillion, invest in creating a whole family of new clean sheet ISAs, each with different targets?

Because funds get mismanaged all the time. There are tons of architects already available with experience in ARM architecture design. RISC-V is immature and no amount of money is going to make it compete with ARM unless everybody simply decides to ditch ARM and go through the painful phase of "RISC-V"ing every little thing available for ARM.

Probably the only companies who could do RISC-V somewhat right are Intel, AMD, Apple and Nvidia. Without their full weight behind RISC-V, I don't see it going much of anywhere. It will remain mostly niche.

 

[Io Magnesso]

Because funds get mismanaged all the time. There are tons of architects already available with experience in ARM architecture design. RISC-V is immature and no amount of money is going to make it compete with ARM unless everybody simply decides to ditch ARM and go through the painful phase of "RISC-V"ing every little thing available for ARM.

Probably the only companies who could do RISC-V somewhat right are Intel, AMD, Apple and Nvidia. Without their full weight behind RISC-V, I don't see it going much of anywhere. It will remain mostly niche.

No, it doesn't have to be just a big big company
There are areas where ARM was the main battlefield, such as the microcontroller and in-vehicle fields.
For example, there is a famous place such as Renesas.