Discussion RISC V Latest Developments Discussion [No Politics]

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DisEnchantment

Golden Member
Mar 3, 2017
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Some background on my experience with RISC V...
Five years ago, we were developing a CI/CD pipeline for arm64 SoC in some cloud and we add tests to execute the binaries in there as well.
We actually used some real HW instances using an ARM server chip of that era, unfortunately the vendor quickly dumped us, exited the market and leaving us with some amount of frustration.
We shifted work to Qemu which turns out to be as good as the actual chips themselves, but the emulation is buggy and slow and in the end we end up with qemu-user-static docker images which work quite well for us. We were running arm64 ubuntu cloud images of the time before moving on to docker multi arch qemu images.

Lately, we were approached by many vendors now with upcoming RISC-V chips and out of curiosity I revisited the topic above.
To my pleasant surprise, running RISC-V Qemu is smooth as butter. Emulation is fast, and images from Debian, Ubuntu, Fedora are available out of the box.
I was running ubuntu cloud images problem free. Granted it was headless but I guess with the likes of Imagination Tech offering up their IP for integration, it is only a matter of time.

What is even more interesting is that Yocto/Open Embedded already have a meta layer for RISC-V and apparently T Head already got the kernel packages and manifest for Android 10 working with RISC-V.
Very very impressive for a CPU in such a short span of time. What's more, I see active LLVM, GCC and Kernel development happening.

From latest conferences I saw this slide, I can't help but think that it looks like they are eating somebody's lunch starting from MCUs and moving to Application Processors.
1652093521458.png

And based on many developments around the world, this trend seems to be accelerating greatly.
Many high profile national and multi national (e.g. EU's EPI ) projects with RISC V are popping up left and right.
Intel is now a premium member of the consortium, with the likes of Google, Alibaba, Huawei etc..
NVDA and soon AMD seems to be doing RISC-V in their GPUs. Xilinx, Infineon, Siemens, Microchip, ST, AD, Renesas etc., already having products in the pipe or already launched.
It will be a matter of time before all these companies start replacing their proprietary Arch with something from RISC V. Tools support, compiler, debugger, OS etc., are taken care by the community.
Interesting as well is that there are lots of performant implementation of RISC V in github as well, XuanTie C910 from T Head/Alibaba, SWerV from WD, and many more.
Embedded Industry already replaced a ton of traditional MCUs with RISC V ones. AI tailored CPUs from Tenstorrent's Jim Keller also seems to be in the spotlight.

Most importantly a bunch of specs got ratified end of last year, mainly accelerated by developments around the world. Interesting times.
 

naukkis

Golden Member
Jun 5, 2002
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Power8?

Power9?

Power10?

Yeah I have missed that they have done split register file design. Didn't find yet information whether they support register-register moves and front-end logic to fully target single-tread performance or is that split only made for SMT threads.

IBM also clearly presents that they are using virtual-address based tagging for both L1i and d.
 

LightningDust

Member
Sep 3, 2024
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Yeah I have missed that they have done split register file design. Didn't find yet information whether they support register-register moves and front-end logic to fully target single-tread performance or is that split only made for SMT threads.

IBM also clearly presents that they are using virtual-address based tagging for both L1i and d.

On P9 and P10, a single thread has access to all four execution slices and their history buffers. There's frontend instruction steering logic and a small penalty for cross-slice dependencies.

P7 and P8 did not have the full scheduling resources available to a single thread, though they do make all backend resources available in ST mode - a single thread could dispatch to either integer cluster.
 

Gideon

Platinum Member
Nov 27, 2007
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Ian has a thread on the subject:


And the whole event is watchable here:


Overall I'm quite impressed with their Open Source claims (including hardware). We should get a lot more info Q2/Q3.

I really hope someone takes their RISC-V core desing and makes a full-fledged desktop CPU from that. But it will take a while (Tenstorrent only has GDDR memory controllers etc, etc)

Overall I say it's quite impressive one can just buy their stuff from their shop, put it in their computer, download open-source drivers and all of it just works
 
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Gideon

Platinum Member
Nov 27, 2007
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Ian actually has a very interesting interview video as well:


Well worth a watch. Damn Tenstorrent seems to be really shaking things up in the next X years
 

soresu

Diamond Member
Dec 19, 2014
3,777
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Ian has a thread on the subject:


And the whole event is watchable here:


Overall I'm quite impressed with their Open Source claims (including hardware). We should get a lot more info Q2/Q3.

I really hope someone takes their RISC-V core desing and makes a full-fledged desktop CPU from that. But it will take a while (Tenstorrent only has GDDR memory controllers etc, etc)

Overall I say it's quite impressive one can just buy their stuff from their shop, put it in their computer, download open-source drivers and all of it just works
Loooool Keller burned Apple good:

"we named it Metalium because somebody trademarked Metal"

reaction-black.gif
 
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NostaSeronx

Diamond Member
Sep 18, 2011
3,803
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First offshoot of Xiangshan, Kunminghu (XSv3).

"借助于香山昆明湖出色的架构和微架构基础,进迭时空开展了X200的研发工作,并实现了对第二代处理器核X100的大幅性能提升。当前,X200已经完成了代码开发并进入了持续的PPA优化阶段,预计将在2025年Q4季度研发完毕,基于X200的高性能计算芯片将在2026年底面市。"
With the excellent architecture and microarchitecture foundation of Xiangshan Kunming Lake, the X200 research and development work has been carried out in the past and the second-generation processor core X100 has been greatly improved. At present, the X200 has completed the code development and entered the continuous PPA optimization stage, which is expected to be completed in the fourth quarter of 2025, and the X200-based high-performance computing chip will be available by the end of 2026.

RVA25=RVA23.2
 
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camel-cdr

Member
Feb 23, 2024
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I ask Greg a few things about Veyron afterward:

They can fuse non-adjacent instructions, so no compiler support is needed.

LMUL is handled late in the pipeline, so LMUL>1 instructions are scheduled as single instructions and only split at issue.