Discussion RDNA 5 / UDNA (CDNA Next) speculation

[soresu]

Pretty much, when do we get the babby version of OAM on desktop?

Bear in mind that OAM is designed with horizontally oriented (components and sockets facing up) PCBs stacked vertically in racks.

Moving to tower cases alleviated the desk space problem with desktop computing and replaced it with another in the form of PCB physical design constraints in vertically oriented PCBs and heavy attached heatsinks pulling CPU sockets and PCIe slots down with gravity.

I can't imagine what kind of physical demands you would put on a PCB from a full load of 8 OAM accelerators in that kind of configuration.

 

[soresu]

The AT0 XL entry in the table with 36GB GDDR7 clearly says "Desktop Gaming".

I wonder if AT is supposed to be code for Amethyst?

With Sony and AMD so publicly collaborating on ML/FSR and RDNA5 it wouldn't be a huge stretch for that generation of GPUs to be codenamed for the collaboration project already named.

 

[marees]

I wonder if AT is supposed to be code for Amethyst?

With Sony and AMD so publicly collaborating on ML/FSR and RDNA5 it wouldn't be a huge stretch for that generation of GPUs to be codenamed for the collaboration project already named.

Probably a star / constellation that begins with A & contains T

 

[soresu]

Probably a star / constellation that begins with A & contains T

Antares is already taken by MI300 so unless it's Alpha Tauri that seems unlikely.

Especially as Alpha Tauri is just another name for Aldebaran which was the codename for MI200.

Amethyst makes a lot more sense, and it's not like they have always used star names.

 

[Kepler_L2]

Such a 192 CU chip will definitely be faster than a 5090, when a 5090 is ~1.8x as fast as a 9070 XT with 64CU. Would it be 1.3x / 1.5x / 1.8x faster? We will see.

AT3 will probably feature 36CU and 128bit with 1x SE (according to huge SE spculation from Kepler_L2).
But I do not like the 12 GByte AT2 version. I would rather like to see 72 / 64 / 54 CU with 18 / 18 / 15 GByte.

I wouldn't take the cutdown SKU lineup as gospel at this point, AMD very often plans for very aggressive CU/bus width/mem speed cutdown SKUs that they either cancel or end up upgrading due to lack of competitiveness (e.g. Navi21 originally had a 54 CU/192-bit card planned, Navi33 had a 24 CU/96-bit card planned, etc.)

 

[Kepler_L2]

Normally, yes, but is it in this case? Why waste silicon on a feature that's only for some sort of enterprise/niche audience. Thats' why I hypothesized that it's a combo of two cut-down dies (each of which has dual VCNs) with something like 90-ish CUs and 256 bit bus linked via something like the MI3xx or other MCM devices.

They aren't wasting anything, the CGVDI SKUs are using a larger MID with PCIe Gen6 and more VCN, gaming SKUs use a smaller/cheaper MID.

 

[GodisanAtheist]

It's already been touched on in this thread I think, but if AMD is going after the 6090 it's doing it with 2x ~400mm2 dies rather than one 800mm2 die.

IMO AMD's N51 (or whatever) die will be 96cu and for the top end part we'll get two N51 dies that appear as one 192cu monster.

A little different from the GCD/MCD split of N31 but built on what was learned there.

What's the point of doing all that GPU chiplet R&D if it doesn't pay off...

 

[Kepler_L2]

Antares is already taken by MI300 so unless it's Alpha Tauri that seems unlikely.

MI300 codename is Aqua Vanjaram

 

[soresu]

MI300 codename is Aqua Vanjaram

Huh, I thought you were making a joke for a second but it's real.

But I've also seen Antares in reference to it.

Is this just µArch family vs SKU codename issue?

 

[Kepler_L2]

Huh, I thought you were making a joke for a second but it's real.

But I've also seen Antares in reference to it.

Is this just µArch family vs SKU codename issue?

I don't know whoever spread the Antares codename but it's not accurate.

 

[SolidQ]

MO AMD's N51 (or whatever) die will be 96cu and for the top end part we'll get two N51 dies that appear as one 192cu monster.

I think, we will get clearer information in the fall

 

[marees]

MI300 codename is Aqua Vanjaram

This is a made up name used in drivers & other linux documentation right

The true nickname I guess would be something based on a star name

I am guessing vanjaram refers to a fish name ??

 

[adroc_thurston]

IMO AMD's N51 (or whatever) die will be 96cu and for the top end part we'll get two N51 dies that appear as one 192cu monster

Nope.
Monodies all the way through.

 

[branch_suggestion]

It's already been touched on in this thread I think, but if AMD is going after the 6090 it's doing it with 2x ~400mm2 dies rather than one 800mm2 die.

Nobody is using CoWoS in client. Plus AT0 should end up at 550-600mm^2.

A little different from the GCD/MCD split of N31 but built on what was learned there.

That was a stopgap and what was learnt there is going into Zen6.

What's the point of doing all that GPU chiplet R&D if it doesn't pay off...

The payoff is still to come, lots of chiplet gaming GPU patents still coming out.
Just need to wait for GFX14.

 

[adroc_thurston]

I wouldn't take the cutdown SKU lineup as gospel at this point, AMD very often plans for very aggressive CU/bus width/mem speed cutdown SKUs that they either cancel or end up upgrading due to lack of competitiveness (e.g. Navi21 originally had a 54 CU/192-bit card planned, Navi33 had a 24 CU/96-bit card planned, etc.)

Well, not quite.
Gigachops being dead outside of specific SRP fillers (like 9070GRE) are a result of TSM yields being generally very good.

 

[dangerman1337]

I suspect AT0 is 192 CUs, 512-bit bus memory with 64MB L2 Cache and I think AT2 is 72 CUs, 192-bit bus memory with 24MB L2 Cache if multipliers and scaling applies (72 x 2.666666666666667 = 192 CUs, same with 192 x 2.666666666666667 = 512 and 24 x 2.666666666666667 = 64).

Why there is no AT1 with 96 CUs and 256-bit bus w/ 32MB of L2 Cache is weird though which I agree with @Kepler_L2 on as stated on Twitter. And what AT3 is (if AT2 is chopped into 128-bit bus, then would AT3 be 96-bit? would have to be 225 USD WW max)?

I mean overall:

1. AT0 - 192 CUs, 512-bit Memory Bus, 64 MB L2 Cache.
2. AT1 - 96 CUs, 256-bit Memory Bus, 32 MB L2 Cache.
3. AT2 - 72 CUs, 192-bit Memory Bus, 24 MB L2 Cache.
4. AT3 - 48CUs, 128-bit Memory Bus, 16 MB L2 Cache.

Makes a lot of sense but AMD indicates my hypothetical AT1 & 3 ain't happening? I would think a 144CU, 384-bit bus with 48MB L2 Cache could fit in there (so AMD fits each die into 50, 60, 70, 80 & 90 classes neatly) but I think due to yields and design costs it's better to cut down AT0 whenever possible since that'll be big.

Regardless I am glad AMD seems really going against 6090/6090 Ti (full die probably 288 SMs thinking logically) this gen because with likely FSR 5 after FSR 4's Redstone update seems something they should and will be doing than chickening out because RTX 60 will likely be a die shruken Blackwell with a few tweaks architecture wise to work out current kinks.

 

[jpiniero]

Regardless I am glad AMD seems really going against 6090/6090 Ti (full die probably 288 SMs thinking logically) this gen because with likely FSR 5 after FSR 4's Redstone update seems something they should and will be doing than chickening out because RTX 60 will likely be a die shruken Blackwell with a few tweaks architecture wise to work out current kinks.

That's the other thing about the slide... even with some AI angle, I'm just not buying them doing a $1000+ gaming GPU with a bit of "AI" sales on the side.

 

[Kepler_L2]

I suspect AT0 is 192 CUs, 512-bit bus memory with 64MB L2 Cache and I think AT2 is 72 CUs, 192-bit bus memory with 24MB L2 Cache if multipliers and scaling applies (72 x 2.666666666666667 = 192 CUs, same with 192 x 2.666666666666667 = 512 and 24 x 2.666666666666667 = 64).

Why there is no AT1 with 96 CUs and 256-bit bus w/ 32MB of L2 Cache is weird though which I agree with @Kepler_L2 on as stated on Twitter. And what AT3 is (if AT2 is chopped into 128-bit bus, then would AT3 be 96-bit? would have to be 225 USD WW max)?

I mean overall:

1. AT0 - 192 CUs, 512-bit Memory Bus, 64 MB L2 Cache.
2. AT1 - 96 CUs, 256-bit Memory Bus, 32 MB L2 Cache.
3. AT2 - 72 CUs, 192-bit Memory Bus, 24 MB L2 Cache.
4. AT3 - 48CUs, 128-bit Memory Bus, 16 MB L2 Cache.

Makes a lot of sense but AMD indicates my hypothetical AT1 & 3 ain't happening? I would think a 144CU, 384-bit bus with 48MB L2 Cache could fit in there (so AMD fits each die into 50, 60, 70, 80 & 90 classes neatly) but I think due to yields and design costs it's better to cut down AT0 whenever possible since that'll be big.

Regardless I am glad AMD seems really going against 6090/6090 Ti (full die probably 288 SMs thinking logically) this gen because with likely FSR 5 after FSR 4's Redstone update seems something they should and will be doing than chickening out because RTX 60 will likely be a die shruken Blackwell with a few tweaks architecture wise to work out current kinks.

Configs may not be final, I can see AT0 being downgraded to 160 CU or AT2 being upgraded to 80CU and 256-bit for example.

 

[marees]

1. AT0 - 192 CUs, 512-bit Memory Bus, 64 MB L2 Cache.
2. AT1 - 96 CUs, 256-bit Memory Bus, 32 MB L2 Cache.
3. AT2 - 72 CUs, 192-bit Memory Bus, 24 MB L2 Cache.
4. AT3 - 48CUs, 128-bit Memory Bus, 16 MB L2 Cache.

AT2 = 9070xt & 6800xt successor is the most profitable market for AMD

AT3 = entry level card. Has to be manufactured to stay in the business

AT0 = Radeon VII like card. Mostly for non-gaming consumers

AT1 = makes no business sense. Guaranteed to lose on sales to 6080 & 6080 super & 6080 ti & 6080 ti super

 

[marees]

AT2 = 9070xt & 6800xt successor is the most profitable market for AMD

AT3 = entry level card. Has to be manufactured to stay in the business

AT0 = Radeon VII like card. Mostly for non-gaming consumers

AT1 = makes no business sense. Guaranteed to lose on sales to 6080 & 6080 super & 6080 ti & 6080 ti super

On top of this

AT2 = die shared with xbox next

AT3 = die shared with halo ??

 

[adroc_thurston]

Radeon VII like card.

Uh, no?

Mostly for non-gaming consumers

Yeah but it'll undergo a mahou shoujo transformation into a gaming flagship if NV is weak enough.

AT3 = die shared with halo

no, laptop SOCs are wholly bespoke parts.
You can't share memory IP between GDDR and LPDDR.

 

[jpiniero]

Yeah but it'll undergo a mahou shoujo transformation into a gaming flagship if NV is weak enough.

See I think the 6090 (and to an extent the 3 die products) should be a decent improvement... but the lower tier products I'd expect nVidia to skimp to maintain margins because of TSMC's wafer prices.

 

[Claudiovict]

Regardless I am glad AMD seems really going against 6090/6090 Ti (full die probably 288 SMs thinking logically) this gen because with likely FSR 5 after FSR 4's Redstone update seems something they should and will be doing than chickening out because RTX 60 will likely be a die shruken Blackwell with a few tweaks architecture wise to work out current kinks.

Really 288 SMs? Thats 1,53x the SM count on RTX 6000 Pro

 

[adroc_thurston]

full die probably 288 SMs thinking logically

How the hell do I ship shit much with 30% shrink

 

[ToTTenTranz]

AT0 = Radeon VII like card. Mostly for non-gaming consumers

AT0 XL is a gaming card. If we're to believe the list that first named the AT0 codename, then we should believe what the list says.