Originally posted by: kobymu
Originally posted by: SexyK
They key factor holding back Fusion-type graphics is memory bandwidth. People in the 8600 thread are crucifying the card because it has a 128-bit memory bus at ~2GHz memory clock which is around 32GB/s of memory bandwidth. Currently, top of the line DDR2 modules offer around 8.5GB/s of memory bandwidth. How do you foresee a Fusion-type integrated GPU achieving anywhere near the 86+GB/s memory bandwidth of an 8800GTX, let along the 32GB/s of an 8600GTS? The only option would be to integrate high-speed GDDR4 into the motherboard which would drive up costs and leave you stuck with the same memory speed/type even if you threw in a new GPU. For now, expansion slots for graphics memory are out of the question because the noise introduced by the slot interface prohibits such high-speed operation. Additionally, the cost of integrating 384 or 512 bit memory slots onto a motherboard would be prohibitive even if 2GHz operation were possible.
The thing is you don?t see
that kind of bandwidth in CPU <--> main memory (pipeline sub-system / FSB) because CPU don?t
need that kind of bandwidth, in 9 out of 10 scenarios CPU needs low latencies.
Nothing is stopping Intel/AMD from providing such bandwidth, nothing! It was just never needed before, look at quad-core for crying out load, even it only reaches bandwidth bottleneck in certain server application. That?s
4 CPUs using the same pipeline to the memory subsystem, and the only reason Intel/AMD don?t provide such bandwidth in today CPUs is that it will add cost to the CPUs even when it is not
needed in 90%+ of its cycles.
Latency, well that is a different story, there are
hard technology limitation there, bandwidth not so much.
Since you brought out cost as an argument then please indulge me, how much does a hardcore gamer system cost now, and how much do you think that a high performances fusion system will cost?
Where do you see the memory bandwidth coming from for a top-end integrated graphics solution?
http://www.sun.com/processors/UltraSPARC-T1/details.xml
Integration
* Up to 8 cores, 4 threads per core
* *4* 144-bit DDR2-533 SDRAM interfaces
- Quad error correct, octal error detect, chipkill ECC
* 4 DIMMS per controller - 16 DIMMS total
* Optional 2-channel operation mode
* JBUS Interface
- 3.1 GB/sec peak effective bandwidth
- 128 bit address/data bus
- 150 - 200 MHz operation
Take the underlying parts and let math do the rest of the job (replace DDR2-533 with DDR3-1066 and 150 ? 200
MHz with 2 - 2.5
GHz).
This is just to provide you with a thread of thought.