Discussion Qualcomm Snapdragon Thread

[SpudLobby]

Hypothetical Question

Let's take 2 CPUs. They both use the identical core architecture/caches. Overall multicore performance is also identical (4.4×10=44, 4.0×11=44).

(A) 10 cores @4.4 GHz using HP library

(B) 11 cores @4.0 GHz using HD library

Which solution is better in terms of PPA? I am curious which will take up more die area and which will be more efficient at multicore performance.

It’s not just a library thing afaict, you have connector/domino logic or other physical design stuff that inflates area. That and the literal layout of the internal blocks changes the higher speeds you need.

I don’t think btw that even AMD uses HP libraries for their mobile CPU’s even on Zen 4. If you read, they used HD libraries with Zen 2 and probably Zen 3 but relaxed track heights. Basically N7 was hitting 4GHz+ on HD cells with some relaxed stuff.

Whatever they did or do I will assure you it won’t be that bloated relative to AMD or Intel’s big designs. It will be big of course but that’s because the architecture will be big.

 

[SpudLobby]

If the rumor that Apple is throwing in the towel on a 5G modem is true, what good is a 6G modem going to do (on a side note I'm skeptical 6G will even be used in phones) A 6G modem still has to support 5G/LTE, and it isn't as though 6G will be easier (if their issues are partly hardware related) and on the baseband side LTE/5G/6G it doesn't matter because you retain all the complexities of interfacing with thousands of carriers over hundreds of bands in hundreds of countries.

Those rumors may be false as it turns out Apple did produce some iPhone 15 test models using their own modem. Now I imagine things went badly enough when they left Apple HQ with those test phones (probably mostly when they left the US) that they felt they had no choice but to take the option to extend the Qualcomm deal. But it is hard to imagine things went SO badly they canceled the entire project!

But if Apple really truly can't get their own modem working they should call up Mediatek and offer to buy their modem. Not to buy modems from them, but to buy their modem - give Apple all the chip designs, baseband software, and licenses to all of Mediatek's cellular related patents (or better yet for Apple's purposes make Apple 50% owner of those patents so they are in a better licensing position vis a vis Qualcomm) and Apple can use Mediatek's designs as a starting point for their modem. Mediatek would continue development as before, and the two projects would slowly diverge. Sort of like forking an open source software project. Surely Mediatek would be willing to take a billion or two off Apple's hands at no real cost to them - and even ignoring the cash it would be a win for them as doing that would hurt their biggest competitor, Qualcomm.

I agree in the event they can’t do it on their own, going to meet MediaTek in the middle would be a great move one way or another.


But again this rumor is probably BS. I think they’ve just delayed it and it’ll be a SE thing first and then 2026/2027 for other phones.

https://x.com/dylan522p/status/1729940407310807417?s=46

https://x.com/dylan522p/status/1729971960355127736?s=46

What Dylan said is absolutely correct based on a plain read of Qualcomm’s modem pricing even to Apple. It’s ludicrous.

Though what occurs to me is that even when Apple used Intel modems for a while from the 7 to 11 Pro, the performance was inferior on reception, speed, and battery to a degree, but it wasn’t significant enough to get people to leave for Android.

Realistically as long as they do better than that on a relative measure for reception and battery life, they’ll be fine. They won’t beat QC overall obviously and I think they know that.

The problem is that it’s just hard to even get to a B- it seems which checks out, because RF is just very challenging.

 

[FlameTail]

I wonder if there will be cut down versions of the X Elite with perhaps 10 or 8 CPU cores and a cut down GPU as well.

TSMC N4P yields are excellent but not perfect.

 

[SpudLobby]

I wonder if there will be cut down versions of the X Elite with perhaps 10 or 8 CPU cores and a cut down GPU as well.

TSMC N4P yields are excellent but not perfect.

Well we thought that initially but it doesn’t seem like it. Seems like they canceled that.

 

[FlameTail]

Well we thought that initially but it doesn’t seem like it. Seems like they canceled that.

Then how are they going to do any product segmentation whatsoever?

 

[SpudLobby]

Then how are they going to do any product segmentation whatsoever?

They’re not. The SoC can be used in anything from a 10W to 45W design. I doubt long term they’ll stick to this, but it works for now

 

[FlameTail]

I'd be very surprised if otherwise.

Even Apple does that kind of segmentation.

 

[SpudLobby]

I'd be very surprised if otherwise.

Even Apple does that kind of segmentation.

If that were the case they’d have announced it though.

I thought the same thing and the rumors suggested as much and then they just announced one single part.

 

[SpudLobby]

My guess is the same reason they went for 12 cores to begin with — they have lightning in a bottle and they want to be able to win or genuinely compete on the bread and butter relative to the M2/3, AMD’s Zen 4 and Zen 5 mainstream 6-12 (5 will have 12 cores) SKUs, and any Intel BS.

With one dominant SKU initially they basically gatekeep the narrative towards performance with a side of Apple’s/Arm esque efficiency.

But it could just be that yields are good enough to where Adreno is already somewhat cut down to esnure some floor of function for every unit and that nets them 90% of models, and then anything with effed up cores they throw out.

IDK.

To me though yields surely would mean they could disable a few cores or something but they have not said a word in that direction

 

[FlameTail]

Firstly, on yields - today's N3 has the same defect density (D0) as N5 did at this current stage of development and production, and TSMC states they have 'industry leading' yield in high volume production. They expect N3 defect rates to track with N5 as expected and reach parity in due course. Note that N5 defect rates run to around 0.07 per cm2 (or 40-45 per wafer).

Source: https://morethanmoore.substack.com/p/tsmc-oip-forum-fabs-n3n2bspn

There is the information about N5 (and by extension N4)'s defect rate. What can we make of that in regards to the X Elite?

 

[FlameTail]

Not sure which thread to post this in. Guess I'll do it here since the original reddit thread concerns the Snapdragon 8 Gen 3.

https://www.reddit.com/r/Android/comments/18pmbxp/_/ker646u

Can someone here respond to what this comment is saying?

 

[SpudLobby]

M

Not sure which thread to post this in. Guess I'll do it here since the original reddit thread concerns the Snapdragon 8 Gen 3.

https://www.reddit.com/r/Android/comments/18pmbxp/_/ker646u

Can someone here respond to what this comment is saying

This guy is completely full of crap. No you cannot get a Ryzen chip to average 5W running 8 cores at 3GHz (actual) on an actual meaningful workload. If you measured with the full board power from the power delivery and included DRAM then it’s an even bigger “lmfao no”.

Everything he says is just garbage or bizarrely weird technicalities. Like this is straight up babble.

Flame you gotta just tune these people out lol. This isn’t worth anyone’s time

 

[SpudLobby]

Source: https://morethanmoore.substack.com/p/tsmc-oip-forum-fabs-n3n2bspn

There is the information about N5 (and by extension N4)'s defect rate. What can we make of that in regards to the X Elite?

That’s really low. N5 has the best yield of any leading TSMC process and N4 is even better. 40-45 for an entire wafer is great.

 

[SpudLobby]

That’s really low. N5 has the best yield of any leading TSMC process and N4 is even better. 40-45 for an entire wafer is great.

A 300mm wafer with a QC die 12x14mm and with the standard scribe BS yields 359 dice per wafer. With 40 defects for the entire wafer, worst case — assuming all end up placed on individual dice (no double hits) and none are salvageable with redundancies (see for ex it hits SRAM I think sometimes), you have a catastrophic yield rate of 88.9%. I don’t know how the redundancy stuff works with catastrophic defects though and for a complicated SoC.

But nearly 90% is really good.

 

[SpudLobby]

Die Per Wafer (free) Calculator - Trusted by Amkor and GF

How can you calculate the number of dies per wafer? A free online tool, DPW equation and reference to two other DPW calculators. Trusted by Amkor and GF.

anysilicon.com

 

[Doug S]

If that were the case they’d have announced it though.

I thought the same thing and the rumors suggested as much and then they just announced one single part.

Why would they have announced it now, for a product that's IIRC not coming out for six months?

The existence of cut down versions is far more about market segmentation than yield anyway. Look at the area consumed by the CPU and GPU in Apple Silicon versus the total die area. The overwhelming majority of die area is "other", so that's where most defects will hit - and most of that is not redundant, i.e. they aren't selling chips missing a NPU core or a memory controller. If you look at Apple's M1 & M2 families, I'll bet 90-95% of the ones sold with a "cut down" config are actually fully functional.

You can see that even more obviously from M3. That's getting made on a far worse process that has a defect rate 3-4x that of M1 & M2. If they were market segmenting based on yield the "cut down" configs would be cut down further and/or there would be several less configs available. The only difference is that instead of 95% of the lesser chips being fully functional with M3 would be more like 60-70%.

 

[SpudLobby]

Why would they have announced it now, for a product that's IIRC not coming out for six months?

The existence of cut down versions is far more about market segmentation than yield anyway. Look at the area consumed by the CPU and GPU in Apple Silicon versus the total die area. The overwhelming majority of die area is "other", so that's where most defects will hit - and most of that is not redundant, i.e. they aren't selling chips missing a NPU core or a memory controller. If you look at Apple's M1 & M2 families, I'll bet 90-95% of the ones sold with a "cut down" config are actually fully functional.

You can see that even more obviously from M3. That's getting made on a far worse process that has a defect rate 3-4x that of M1 & M2. If they were market segmenting based on yield the "cut down" configs would be cut down further and/or there would be several less configs available. The only difference is that instead of 95% of the lesser chips being fully functional with M3 would be more like 60-70%.

Ya of course it’s segmentation and they’ll charge more for the 12c variant if they were doing that.

Ya agree re Mx stuff. There’s no reason to literally believe every one of those dice just magically lines up with defects to meet demand or whatever. They cut them down and segment, assure some similar product for all. Apple does this even with voltages for their CPUs (forget where I heard) iirc — they’ll set them all at the same bar within some tolerance, you don’t really get a lottery functionally like you will with Intel/AMD.



RE: QC: why would they have not announced it? They specifically even mentioned this part scaling from fanless to 45W with the changes all taking place OEM-side — they’ve been fairly straightforward about this being one SKU. I mean they gave it a name and everything here, it’s not like they just said “hey here’s our core” and did one technical demo leaving us to ponder what products might incorporate it. Now, “X Elite” to me might leave the doors open for some qualifiers but I think if they really had multiple variants they’d have announced it.



And the six months here: it’s an unusual circumstance. They’re doing hands-on, talking about the benchmarks explicitly. They obviously wanted to share this in October and decided to do so anyways even with the further delay for probably investor/stock reasons.

 

[SpudLobby]

I think in the future they absolutely will segment, and might even have two separate dice. But for now I think they really just said “keep it simple”.

I don’t really think it’s ideal, I would segment some and hammer home efficiency even further, but my guess is they want to have one simple part that’s known for 12C and throughput + efficiency, just because or how tattered their reputation is thus far.

That’s the only thing, besides the idea they will unveil variants later, that makes sense to me.

 

[FlameTail]

I think in the future they absolutely will segment, and might even have two separate dice.

I think more than 2 dice would be essential.

3 would be great. To address the market all the way from low end windows laptops/chromebooks to high end Pro machines.

 

[FlameTail]

Past Snapdragon Summits:

2020 : Dec 1, Dec 2
2021 : Nov 30, Dec 1
2022 : Nov 15, Nov 16, Nov 17
2023 : Oct 25, Oct 26, Oct 27

Anyone notice a pattern? Where is this heading?

Qualcomm is pulling in the Snapdragon Summit (and the products that are announced with it) to earlier in the year.

 

[soresu]

View attachment 90945
Past Snapdragon Summits:

2020 : Dec 1, Dec 2
2021 : Nov 30, Dec 1
2022 : Nov 15, Nov 16, Nov 17
2023 : Oct 25, Oct 26, Oct 27

Anyone notice a pattern? Where is this heading?

Qualcomm is pulling in the Snapdragon Summit (and the products that are announced with it) to earlier in the year.

Stop I beseech you before you stumble down the path into numerology and get permanently lost 😅

There's nothing weird about it, a similar thing happened with the ARM IP announcements getting steadily later in the year over the last decade.

 

[NTMBK]

I wonder if Windows 12 will contain scheduler and other optimisations for the X Elite chip.

X Elite will debut with Windows 12.

I hope there's a way to strip all that "AI" garbage out of Windows 12. I expect it to be just as useful to my life as Cortana was in Windows 10, i.e. not at all. It's just one more way for the corporations to hoover up your data.

 

[FlameTail]

Guys, we have talked about this previously. What is the composition of the 42 MB Cache mentioned here?

We do know one fact: 36 MB of that is L2; with 12 MB per cluster of 4 cores. This was mentioned by a Qualcomm Person in an interview.

So then what about the remaining 6 MB?

Is it L1? L3? SLC?

If the 6 MB is L1, then divided across 12 cores it would be 512 KB per core. That is a huge amount of L1, far bigger than even Apple's P cores. So I don't think the 6 MB is the L1.

It could be 6 MB of L3. This is again a possibility, but I see no reason for them to have 6 MB of L3. FWIW the L2 cache slices are far bigger in size at 12 MB each. Also we know the Oryon CPU was designed by ex-Apple engineers, and we know Apple's CPU design does not contain an L3. Hence the 6 MB is probably not an L3.

That leaves us with the SLC. At first 6 MB of SLC sounds improbable, as even Qualcomm's mobile chips have more SLC.

But consider the Apple M3:

It has only 8 MB of SLC. And yes, that's less than recent A chips.

We know Qualcomm loves to cut on the cache. Indeed, the Oryon CPU has 12 MB of L2 per cluster, which is 3/4th of Apple's 16 MB per cluster. So reasonably straightforward- 3/4th of 8 MB is 6 MB!

Hence, I believe the 42 MB Total Cache quoted by Qualcomm is 36 MB L2 + 6 MB SLC.

 

[FlameTail]

What are the chances Snapdragon X Elite will be paired with 8 GB RAM?

Personally, I think Qualcomm should impose a restriction on OEMs to not ship devices with 8 GB. Minimum should be 12 GB. 8 GB is really not enough today, and more so in the future. Especially in the $1000+ segment, which I believe the X Elite is targeting.

Intel kinda did this to an extent with Meteor Lake. To advertise Arc Xe Graphics, OEMs need to ship it with a minimum of 16 GB RAM on a 128 bit bus. No 8 GB / single-channel shenanigans.

Intel's slapped a 16GB dual-channel minimum entry requirement on Core Ultra laptops if you want top gaming performance

To get an 'Arc Graphics' sticker, your Core Ultra laptop has to be dual-channel with 16GB of memory.

www.pcgamer.com

 

[Thibsie]

Qualcomm behaves a lot like Apple IMO.
If Apple can do it, Qualcomm can too.
Never underestimate greed.