New Zen microarchitecture details

[Sven_eng]

If the red rectangle is 15mm2 then the die is smaller than 200mm2

It would be nearly 200mm2 exactly.

 

[CatMerc]

My estimations off of the various pictures say 192mm^2 give or take 20mm^2.

 

[Dresdenboy]

Bulldozer die is 315mm2, 25% smaller is 236mm2. Do you believe the 8C ZEN die will be that large ??

That was in relation to XV/BR as we also discussed 28nm.

If the red rectangle is 15mm2 then the die is smaller than 200mm2

Closer. There is one more hint.

 

[Atari2600]

Thats pretty good.

BWE is supposed to be around 245 mm2.

 

[AtenRa]

That was in relation to XV/BR as we also discussed 28nm.

ahh ok

Closer. There is one more hint.

which is ???

 

[CatMerc]

Thats pretty good.

BWE is supposed to be around 245 mm2.

To be fair to BWE, it has four memory channels compared to Ryzen's two.
It also has some fixed function silicon for specific companies large enough to request it (Amazon, Google, etc') that only they can access. We don't know if AMD made any such deals.

And of course, it has two more cores.

Considering Intel's process is supposedly superior in density and performance, that's still quite impressive density on AMD's architecture.

 

[Redentor]

Ryzen is a SoC. BRW-E not.

 

[CatMerc]

Ryzen is a SoC. BRW-E not.

I see where you're coming from, but BWE also has far more PCI-E links coming from the CPU than Ryzen does, so even though Ryzen has some SATA and USB controllers on there, I don't think the SoC aspect of Ryzen costs it anymore transistors than the extra PCI-E lanes from the CPU.

 

[Dresdenboy]

which is ???

Right in the middle of my answer to Shintai.

 

[krumme]

That was in relation to XV/BR as we also discussed 28nm.

Closer. There is one more hint.

Ddr phy area ? Extrapolate from skl and xv?

 

[CatMerc]

Right in the middle of my answer to Shintai.

For the lazy people:

At ~57% the 8C PD's die size, the cost disadvantage per wafer will be alleviated a bit.

Piledriver 8C is 314mm^2.
57% of that is 179mm^2.

 

[leoneazzurro]

In that case the yields, if the cost figures of 18/21$ per piece are right, are between 50% and 60%, possibly they will increase as time passes. In this case the margin if improvement is larger.

 

[CatMerc]

In that case the yields, if the cost figures of 18/21$ per piece are right, are between 50% and 60%, possibly they will increase as time passes. In this case the margin if improvement is larger.

How do you figure?

 

[Dresdenboy]

For the lazy people:

Piledriver 8C is 314mm^2.
57% of that is 179mm^2.

That's it. Of course this is just an estimation.

 

[leoneazzurro]

If a wafer costs around 4K$ and a die costs between 18$-20$, then there should be around 200-220 good dies per wafer. A wafer area is a note number, with around 90% of that area available for dies. If you know the die size, then you can do the math. Given the uncertainty in wafer cost, die cost and die size only a rough number can be estimated. Not that this is the actual truth, it's only a guess based on the number given in this thread.

 

[CatMerc]

If a wafer costs around 4K$ and a die costs between 18$-20$, then there should be around 200-220 good dies per wafer. A wafer area is a note number, with around 90% of that area available for dies. If you know the die size, then you can do the math. Given the uncertainty in wafer cost, die cost and die size only a rough number can be estimated. Not that this is the actual truth, it's only a guess based on the number given in this thread.

Fairly certain a 14nm wafer doesn't cost 4k for AMD. It's probably the price for the foundry to manufacture it, without the cut to make a profit.

It's probably more like 5k.

 

[Sven_eng]

If the L3 cache is 15mm2 and it fits 12x in the die with a little room to spare, it must be above 180mm2?

 

[leoneazzurro]

Fairly certain a 14nm wafer doesn't cost 4k for AMD. It's probably the price for the foundry to manufacture it, without the cut to make a profit.

It's probably more like 5k.

Then yields should be better than that, by 25% (that is 62%-75%)

 

[raghu78]

If the L3 cache is 15mm2 and it fits 12x in the die with a little room to spare, it must be above 180mm2?

I think slightly below 200 sq mm could be the die size.

 

[CatMerc]

I'm assuming Dresdenboy's 15mm^2 is a nice round number for the estimate.
Working off of 179mm^2, I get 13.8mm^2 for L3 of a CCX, which is close enough. I don't know the size of the PHY's, so I don't have other things to compare size to.

:AREA WITH CCX @ 15mm^2:
mm/pixels: 0.0517mm
L3 Height: 4.602mm
L3 Width: 3.259mm
Die Height: 9.409mm
Die Width: 20.628

Die Area: 194.09mm^2


:CCX WITH AREA FROM 179mm^2:
Die Height: 9.036mm
Die Width: 19.808mm
mm/pixels: 0.0496mm
L3 Height: 4.418mm
L3 Width: 3.124mm

L3 Area: 13.801mm^2

 

[Doom2pro]

I'm going for around 195mm2

 

[Dresdenboy]

If the L3 cache is 15mm2 and it fits 12x in the die with a little room to spare, it must be above 180mm2?

An error of a few pixels might quickly add up by repeating it. I'd say, there is at least a 5% error in measurement. It was actually just done in a discussion related to adding L3.

 

[itsmydamnation]

I see where you're coming from, but BWE also has far more PCI-E links coming from the CPU than Ryzen does, so even though Ryzen has some SATA and USB controllers on there, I don't think the SoC aspect of Ryzen costs it anymore transistors than the extra PCI-E lanes from the CPU.

Zen also has to pay a cost for the big inter soc interconnect.
The original rumors had soc level crypto engines on boards ( still unverified)
It also has multiple network interfaces that looks like it might be 2x 10gb ethernet/ 1x ERD infiniband or something ( does anyone know anyone other then mellanox who push ethernet/infiniband capable IP?)

If you look at http://hothardware.com/ContentImages/Article/2470/content/small_broadwell-e-die-shot.jpg you can see both Zen and boardwell E spend significant amount of die in the "uncore". broadwell-E uses it for 2 more memory channels amd uses it to allow them to make one soc that goes from the mainstream enthusiast to the biggest servers.

I assumed a little under 200mm, if 179 is accurate then ~320 dies a wafer is awesome for amd.
I have also loved watching the continued rear guard action of ShintaiDK from IPC to clocks to socket infrastructure he has now had to drop all the way to arguing the viability of a sub 200mm die....... ROFL!

 

[raghu78]

One thing is for sure. This chip is quite small and we have to look back over a decade to see a high end desktop AMD chip below 200 sq mm .

http://www.anandtech.com/show/1676

Phenom, Phenom II X4 and X6 and Bulldozer were all much larger chips. AMD looks to have really hit the sweet spot for performance, die size and power efficiency. AMD can afford to ramp die sizes even by 25-50% over the next 2-3 years as they try to improve IPC, add more functionality (256 bit FP units) and more cores (hopefully).

 

[Sven_eng]

An error of a few pixels might quickly add up by repeating it. I'd say, there is at least a 5% error in measurement. It was actually just done in a discussion related to adding L3.

And I have also included the border multiple times so that could add up to a few mm2 as well. I think 180mm2 must be close to minimum size though but we will see.