Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[511]

Idk if this has been discusses yet, but anyone check out the difference between the X4 on the mediatek 9300 vs the X4 on the mediatek 9400?
20-30% lower core area (both without the L2 cache arrays and with the L2), ~ same Fmax, and ~10-20% lower power on the low end of the curve.
The specFP curve actually shows even worse power numbers than the specint numbers...
View attachment 128242

LPDDR5x 10667 for 9400 BTW also maybe there is a change in finflex configuration if the area is lower.

 

[Geddagod]

LPDDR5x 10667 for 9400 BTW also maybe there is a change in finflex configuration if the area is lower.

The comparison would be between N4P 9300 vs the N3E 9400

 

[511]

The comparison would be between N4P 9300 vs the N3E 9400

Oh 9300N4P than it seems reasonable no cause depending on finflex configuration the PPA can vary by a lot considering this is N5 2-2 fin and N4P 2-2 fin is slightly more performant and a 6% shrink this would line nicely with theory than X4 is using N3E 2-2 fin.
0.72x -> 1.38/1.06 -> 1.3X the size for X4 on N4P vs N3E and 10-20% higher perf seems okay.
This is just my theory BTW.

 

[mikegg]

The contract covers 8 years. Currently Tesla sells 1.8 million cars, when the contract starts, it may be selling 2 million and the end of the contract 4 million.

2 million cars * 8 years = 16 million cars
4 million cars * 8 years = 32 million cars

It does not cover any other needs. Suppose AMD and Tesla agree to make the infotainment systems at Samsung fab (since Musk is getting dirt cheap prices) rather than TSMC.

Suppose Tesla starts to sell robots.

They don't start production until 2028. So that's 5 years of chip making, not 8 years.

Many Teslas in 2028 will still likely be using TSMC chips due to selling older inventory.

 

[RTX]

https://twitter.com/x/status/1952488442702553551

https://twitter.com/x/status/1952489083881803942

https://x.com/hmph29759351/status/1952490080024826046
Is 3nm really that much better than 18A? Should Intel switch over to TSMC after 2028?

 

[511]

https://twitter.com/x/status/1952488442702553551

https://twitter.com/x/status/1952489083881803942

https://x.com/hmph29759351/status/1952490080024826046
https://x.com/Kepler_L2/status/1950631655309537358
Is 3nm really that much better than 18A? Should Intel switch over to TSMC after 2028?

Nope N3E/P is not better than 18A for CPUs to say the least it's better for SoC/GPUs though cause 18A is not optimised for SoC/GPUs 18AP is the one for that hence the use of N3E iGPU Tile in PTL alongside 18A.
For 2028 it depends on who will fund 14A alongside Intel if none they will be relying on TSMC for A14 and beyond.

 

[RTX]

https://twitter.com/x/status/1951718434481299885

Is this the same strategy as AMD?

 

[511]

https://twitter.com/x/status/1951718434481299885

Is this the same strategy as AMD?

Maybe this will help

https://twitter.com/x/status/1952356403185680866

 

[Joe NYC]

https://twitter.com/x/status/1951718434481299885

Is this the same strategy as AMD?

No, AMD is definitely aiming for training, as well as inference.

Training with Mi400 GPUs in 2026.

Inference currently, with Mi300, Mi325, Mi355.

AMD is (or aims to) to outcompete:
H100 with Mi300
H200 with Mi325
B200 with Mi355

The limitation is that the model has to fit within 1 or 8 GPUs, to which AMD can scale to. Models larger than that - that's were NVidia will hold advantage until Mi400.

 

[marees]

No, AMD is definitely aiming for training, as well as inference.

Training with Mi400 GPUs in 2026.

Inference currently, with Mi300, Mi325, Mi355.

AMD is (or aims to) to outcompete:
H100 with Mi300
H200 with Mi325
B200 with Mi355

The limitation is that the model has to fit within 1 or 8 GPUs, to which AMD can scale to. Models larger than that - that's were NVidia will hold advantage until Mi400.

Here is a glimpse of the absurdly powerful AI rack AMD will launch in 2027, complete with Verano CPUs and 144 MI500 AI GPUs​

new system builds on the "Helios" rack shown for 2026, which houses 72 MI400 GPUs across 18 racks. For 2027, AMD is planning an even more expansive setup with 36 racks.

Assuming a similar configuration, the next-gen AI rack could contain 144 GPUs. The Verano platform is expected to maintain the high bandwidth and performance efficiency established by Venice, likely with more memory and compute per rack.

AMD has not officially named its 2027 rack, but we hear it’s being informally referred to in industry circles as a larger-scale continuation of Helios.

Via Tom's Hardware

AMD previews 2027 rack system with 36-rack design powered by Verano and MI500

AMD is focused on driving performance, efficiency and scalability

www.techradar.com

 

[Geddagod]

Oh 9300N4P than it seems reasonable no cause depending on finflex configuration the PPA can vary by a lot considering this is N5 2-2 fin and N4P 2-2 fin is slightly more performant and a 6% shrink this would line nicely with theory than X4 is using N3E 2-2 fin.
0.72x -> 1.38/1.06 -> 1.3X the size for X4 on N4P vs N3E and 10-20% higher perf seems okay.
This is just my theory BTW.
View attachment 128248

I believe it's actually 2-1

Techinsights for Mediatek 9400

Is 3nm really that much better than 18A?

I think N3P and 18A are going to be similar, like TSMC claims.

Should Intel switch over to TSMC after 2028?

If Intel thinks the gap between N2/P and 18AP is large enough that they have to go external for their high end dies, what would the gap be like in 28' with A16 vs just another 18A-P iteration?

 

[511]

I believe it's actually 2-1

Here are the core config and i think

• 1x Arm Cortex-X925, 2MB L2 cache, up to 3.62 GHz 3-2 (needs it to hit high clocks apple also uses this for CPU)
• 3x Arm Cortex-X4, 1MB L2 cache 2-2
• 4x Arm Cortex-A720, 512KB L2 cache 2-1

GPU is definitely 2-2 though

 

[RTX]

Is N3B less dense than N3E logic but denser than N3E in SRAM?

 

[511]

Is N3B less dense than N3E logic but denser than N3E in SRAM?

N3B has the densest SRAM Bitcell even denser than N2 also N3B is slightly more dense than N3E and equally as dense as N3P.

 

[Gideon]

https://twitter.com/x/status/1952488442702553551

https://twitter.com/x/status/1952489083881803942

https://x.com/hmph29759351/status/1952490080024826046
https://x.com/Kepler_L2/status/1950631655309537358
Is 3nm really that much better than 18A? Should Intel switch over to TSMC after 2028?

I have to say it's quite surreal reading @SiliconFly's endless praises to Intel's processes on X/Twitter and then reading threads like this on Reddit:

https://www.reddit.com/r/Semiconductors/comments/1mhvgn8/should_i_remain_in_semiconductors/

Should I remain in semiconductors?​

Context: Intel, PhD, 4 years exp, Yield. High (ish) performer, avoided layoffs.

Intel is in a bad spot right now. I'm...checked out. I loved my job, but lately I've been just coasting by doing the bare minimum. There's zero motivation. Between Intel's bad financials, stock trading at 20 bucks, constant negative press coverage, and a complete and total lack of empathy from senior leadership has made me...well...how does Gen Z put it... "quiet quit."

Thing is, this constant uncertainty of rolling layoffs and the stupid RTO policy has all but made sure that I apply elsewhere (I have very solid family related reasons to be WFH). Question is, is it even worth staying in semiconductors? My degree (materials science) allows me to be a bit more flexible because I did a lot of computational physics/chemistry, so I need not be constrained to semis. Should I even stay? Fabrication in the US seems doomed unless I am ok going to red states (which....fuck that shit, the wife is pregnant and places that give you negative reproductive healthcare are a no go) and places like LAM and AMAT and such are unlikely to let me stay remote or work out of the Boston area where I need to remain for the next several years.
Not even sure what I'm going to do.
Help. Just thinking out loud over here, just gimme your thoughts.

 

[511]

I have to say it's quite surreal reading @SiliconFly's endless praises to Intel's processes on X/Twitter and then reading threads like this on Reddit:

some of his post are best ignored meng is influencing him though that twitter account just states so many rubbish facts it's surreal.

Well LBT is trimming Intel so i don't blame someone wanting to quit and with the crazy stuff going on lol

 

[RTX]

Aren't these bigger than N3E's 2-fin?

I believe it's actually 2-1
View attachment 128288
Techinsights for Mediatek 9400

https://twitter.com/x/status/1950631655309537358

I think N3P and 18A are going to be similar, like TSMC claims.

If Intel thinks the gap between N2/P and 18AP is large enough that they have to go external for their high end dies, what would the gap be like in 28' with A16 vs just another 18A-P iteration?

 

[Hitman928]

Maybe this will help

https://twitter.com/x/status/1952356403185680866

I’ve seen a few of that guy’s posts but I don’t think he’s legit.

 

[Saylick]

Take with a grain of salt?

https://www.reuters.com/world/asia-pacific/intel-struggles-with-key-manufacturing-process-next-pc-chip-sources-say-2025-08-05/

 

[Hitman928]

Take with a grain of salt?

https://www.reuters.com/world/asia-pacific/intel-struggles-with-key-manufacturing-process-next-pc-chip-sources-say-2025-08-05/

Already posted but maybe in a different thread. I think the truth probably lies somewhere in the middle, not as bad as reported but not as good as the “everything is on schedule for normal production yields” story Intel is telling. A key (actual) quote on this from the CFO is this:

In the interview with Reuters, Zinsner disputed these figures and said "yields are better than that." He did not give a number for July or late 2024, and Intel declined to provide this data.
"Our expectation is every month they'll get better and better, such that we're at a yield level that is good for production-level Panther Lake at the end of the year," he said, adding: "I wouldn't say that margins are accretive even at those yield levels, so we still have to make improvement."

Seems he is saying that at launch, the yields on PTL will be bad enough that it will cause the product to have below company average margin, which is already at historic lows, so yield is obviously not where it needs to be.

Tan has tapped supply-chain contacts more than usual for Intel and has given them data to help improve chip yields, Zinsner said.

This also gives credence to the yield story not being as rosy as Intel has claimed, though again, that doesn’t mean it’s as bad as their sources in the article are claiming.

 

[Joe NYC]

Here is a glimpse of the absurdly powerful AI rack AMD will launch in 2027, complete with Verano CPUs and 144 MI500 AI GPUs​

new system builds on the "Helios" rack shown for 2026, which houses 72 MI400 GPUs across 18 racks. For 2027, AMD is planning an even more expansive setup with 36 racks.

Assuming a similar configuration, the next-gen AI rack could contain 144 GPUs. The Verano platform is expected to maintain the high bandwidth and performance efficiency established by Venice, likely with more memory and compute per rack.

AMD has not officially named its 2027 rack, but we hear it’s being informally referred to in industry circles as a larger-scale continuation of Helios.

Via Tom's Hardware

AMD previews 2027 rack system with 36-rack design powered by Verano and MI500

AMD is focused on driving performance, efficiency and scalability

www.techradar.com

BTW, interesting that AMD is moving to N2 with Mi400 while NVidia will use N3 for Rubin.

Maybe NVidia did not order enough capacity early enough

 

[Saylick]

BTW, interesting that AMD is moving to N2 with Mi400 while NVidia will use N3 for Rubin.

Maybe NVidia did not order enough capacity early enough

Probably because there physically isn't enough N2 volume to satisfy Nvidia. Recall that Nvidia is still slapping large monolithic dies together for scale up; not quite a chiplet approach like AMD is doing.

 

[511]

Nvidia need mature yields as well N2 is not that level of maturity yet combined with capacity constraints of N2 it's not suitable.

 

[Joe NYC]

Take with a grain of salt?

https://www.reuters.com/world/asia-pacific/intel-struggles-with-key-manufacturing-process-next-pc-chip-sources-say-2025-08-05/

Seems like some serious binning issues. Qualcomm also had similar binning issues, where only a small percentage of chips reached the desired clock speeds...

 

[Josh128]

Seems like some serious binning issues. Qualcomm also had similar binning issues, where only a small percentage of chips reached the desired clock speeds...

Sounds like Ice Lake all over again. Not sounding good at all.