Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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DisEnchantment

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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

1587737990547.png
N7 performance is more or less understood.
1587739093721.png

This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


1587739615344.png

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE
 
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Geddagod

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My own take on the five nodes in four years strategy was that the internal only 4 nm and 20A were supposed to be the high frequency relaxed geometry nodes. These were being designed for P core die.

With both 14 nm and 10/7 nm they ‘relaxed’ the geometry for higher frequencies in the performance transistors. Focusing on the performance transistors first and exclusive to Intel would give Intel a competitive advantage even as they provided foundry services.

It seems that neither 4 or 20A met their frequency targets.
I think Intel 4 and Intel 20A were nodes that were supposed to pipe clean and have incomplete libraries (only HP) compared to their successors.
However I don't believe Intel 4 and Intel 20A had relaxed geometries in the sense of Intel 14nm or Intel 10nm. Those nodes relaxed gate pitch in order to drive better performance, however Intel 3 does not have denser CGP variants than Intel 4. Intel 3's dense library only decreases cell height, not cell width.
Interestingly enough, Intel hasn't even decreased CGP with even 18A compared to Intel 3.
 
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511

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I think Intel 4 and Intel 20A were nodes that were supposed to pipe clean and have incomplete libraries (only HP) compared to their successors.
However I don't believe Intel 4 and Intel 20A had relaxed geometries in the sense of Intel 14nm or Intel 10nm. Those nodes relaxed gate pitch in order to drive better performance, however Intel 3 does not have denser CGP variants than Intel 4. Intel 3's dense library only decreases cell height, not cell width.
Interestingly enough, Intel hasn't even decreased CGP with even 18A compared to Intel 3.
The increased it lol from 30 to 32 they likely used the relaxation for cost rather than denser design.
 
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Geddagod

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I wasn't told by Intel but an Intel employee or ex Intel employee should I say. It was a big financial issues to ramp that thing.
A big financial issue that Intel would have done anyway in order to ramp 18A.
And something whose costs would have been recouped, very well, since they could then fab a bunch of the 6+8 tiles internally. And given ARL's longer than expected longevity (since PTL-S is not a thing, and PTL mobile is late), it looks even worse now.
The financial excuse, and the "accelerating 18A development" are just excuses from Intel, or Intel employees. 20A would have been unusable and unready, and those delays also impacted 18A's development, hence 18A's perf targets being reduced, and why 18A is coming so late, and officially delayed (risk production supposed to be 2H 24', announced 1H 25').
The increased it lol from 30 to 32 they likely used the relaxation for cost rather than denser design.
They relaxed M0 pitch but gate pitch stayed the same at 50nm.
 

511

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A big financial issue that Intel would have done anyway in order to ramp 18A.
And something whose costs would have been recouped, very well, since they could then fab a bunch of the 6+8 tiles internally. And given ARL's longer than expected longevity (since PTL-S is not a thing, and PTL mobile is late), it looks even worse now also for a flop product a.k.a ARL.
The financial excuse, and the "accelerating 18A development" are just excuses from Intel, or Intel employees. 20A would have been unusable and unready, and those delays also impacted 18A's development, hence 18A's perf targets being reduced, and why 18A is coming so late, and officially delayed (risk production supposed to be 2H 24', announced 1H 25').
So answer me a single 6+8 Tile on 20A vs PTL/WCL/CLW-F/DMR/RRF/Xe3P/NVL SoC on 18A/AP also who will you trust in my case a random guy on a forum or someone you know you are free to believe whatever you want.
Don't forget even though Intel 4/3 are compatible the Metal layers are done different they may be same from designer's standpoint but not necessarily from the foundry standpoint.
 
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Joe NYC

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So answer me a single 6+8 Tile on 20A vs PTL/WCL/CLW-F/DMR/RRF/Xe3P/NVL SoC on 18A/AP also who will you trust in my case a random guy on a forum or someone you know you are free to believe whatever you want.

That Arrow Lake on 20A would be selling for years and could have accelerated transition away from Raptor Lake.

ARL sales on 20A would have been all of 2025 and 2026.
 

511

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That Arrow Lake on 20A would be selling for years and could have accelerated transition away from Raptor Lake.

ARL sales on 20A would have been all of 2025 and 2026.
They did the financial but it didn't work out also the capacity at TSMC would have been wasted for the huge prepayment.
ARL was always N3 until Pat showed up and made optional 20A SKU it was their plan but it didn't pan out they must have had multiple things to look at none of us have that much information.
Also the TSMC Mix would have been higher for ARL vs PTL there is that as well.
 
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Geddagod

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So answer me a single 6+8 Tile on 20A vs PTL/WCL/CLW-F/DMR/RRF/Xe3P/NVL SoC on 18A/AP also who will you trust in my case a random guy on a forum or someone you know you are free to believe whatever you want.
What is the conundrum here? There is no "either/ or". You can have both at the same time.
6+8 tile on 20A, and then you either build out more or transition those 20A fabs to 18A when you ramp PTL and future products, which won't require a bunch of work or money because 18A is only a subnode improvement on 20A.
Intel 18A is not insignificant in volume, nor even capacity constrained for Intel's own internal needs.
Don't forget even though Intel 4/3 are compatible the Metal layers are done different they may be same from designer's standpoint but not necessarily from the foundry standpoint.
Relatively minor changes, and Intel 18A vs 20A had roughly half the perf/watt improvement of Intel 4 vs Intel 3.
Fabbing 20A would always have been worth it, don't swallow Intel's PR marketing spin hook line and sinker.
They did the financial
They have done the financials when they announced the node and the 5N4Y plan too.
They knew the massive PR disaster that cancelling 20A would be.
And again, if it was just financial, how does this explain 18A's lateness, or 18A's cut down perf/watt claims?
also the capacity at TSMC would have been wasted for the huge prepayment.
Or you could just increase volume of ARL/LNL products? It's not as if you would be flooding the market, as ARL/LNL volume as it is today is still not significant compared to RPL. And since a bunch of volume would still be coming from internal, even if you had to lower ASP from increasing ARL/LNL supply, it should still be ok.
Maybe they could have launched ARL halo with a N3 GPU tile as well. Though I'm guessing that didn't get canned for capacity reasons lol.
ARL was always N3 until Pat showed up and made optional 20A SKU it was their plan
ARL on 20A was likely always been a thing in one form or another since conception, or at the very least it would have been considered early in development.
The 6+8 tile was set to launch either with ARL launch, or early 2025 for the non-k skus.
but it didn't pan out they must have had multiple things to look at none of us have that much information.
No, none of us know for certain.
One side of the argument has heaps of more evidence and reasoning behind it though, and it's not the side you are arguing for...
 

511

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What is the conundrum here? There is no "either/ or". You can have both at the same time.
6+8 tile on 20A, and then you either build out more or transition those 20A fabs to 18A when you ramp PTL and future products, which won't require a bunch of work or money because 18A is only a subnode improvement on 20A.
Intel 18A is not insignificant in volume, nor even capacity constrained for Intel's own internal needs.
This is not Intel with tons of money they just took a fab write down that same quarter for Billions of $$$ if it was so easy to fab a product everyone would be fabbing a chip.

It's unlike the time for Palm Cove with a disabled iGPU on messed up 10nm where they had the money for that botched die.

They have done the financials when they announced the node and the 5N4Y plan too.
They knew the massive PR disaster that cancelling 20A would be.
And again, if it was just financial, how does this explain 18A's lateness, or 18A's cut down perf/watt claims?
They did the financial when Their business was at peak but after COVID their revenue dropped massively but not their investment also why is everyone after the 18As lateness? did Intel ever said Products in Q4 24 ? It was H4 24 HVM Readiness as for cut down performance take a look at their claims they said 10-15% PPW over I3 for 20A and 18A was 5-10% over 20A.
This means 15%-26.5% PPW and last I checked 18% is between those numbers. It is the same logic as products launching in H2 25 and than launching on December 31st 2025 is that missed deadline?
Or you could just increase volume of ARL/LNL products? It's not as if you would be flooding the market, as ARL/LNL volume as it is today is still not significant compared to RPL. And since a bunch of volume would still be coming from internal, even if you had to lower ASP from increasing ARL/LNL supply, it should still be ok.
Maybe they could have launched ARL halo with a N3 GPU tile as well. Though I'm guessing that didn't get canned for capacity reasons lol.
For Halo I don't know the reason for the cut maybe they thought it wouldn't sell with half baked drivers.

No, none of us know for certain.
One side of the argument has heaps of more evidence and reasoning behind it though, and it's not the side you are arguing for...
Please show me the evidence that 20A was cancelled because of Yield not financial issues.
ARL on 20A was likely always been a thing in one form or another since conception, or at the very least it would have been considered early in development.
The 6+8 tile was set to launch either with ARL launch, or early 2025 for the non-k skus.
It wasn't
Or you could just increase volume of ARL/LNL products? It's not as if you would be flooding the market, as ARL/LNL volume as it is today is still not significant compared to RPL. And since a bunch of volume would still be coming from internal, even if you had to lower ASP from increasing ARL/LNL supply, it should still be ok.
Maybe they could have launched ARL halo with a N3 GPU tile as well. Though I'm guessing that didn't get canned for capacity reasons lol.
And people are buying more Raptor Lake lol than ARL/LNL combined
 

Geddagod

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Something only a bit related, but also interesting....

Remember a couple months or a year ago when there were rumors that TSMC increased N3 pricing for Intel specifically by a large amount because of them not liking Gelsinger or something?
I heavily doubted it's validity, since I would imagine the pricing details for the node would have been set long before those rumors started swirling around.
However I wonder if the whole N3 wafer deal was to be renegotiated, which gave TSMC the opportunity to change pricing, and that's also why we had Gelsinger visiting Taiwan (along for securing N2 capacity).

I think there's a couple reasons Intel would have had to try to renegotiate N3B wafers with TSMC:
  • timing, N3B was planned to be used by Intel much earlier than they actually ended up using them. It wasn't simply a quarter or two of a shift. This is the least likely reason though IMO, since it would have been apparent the timeline shift was going to happen much earlier than the "tsmc jacks Intel N3 wafer pricing" rumors started coming.
  • asking to increase wafer capacity, since they no longer had 20A 6+8 tiles planned, and they needed to meet the requirements of the market.
  • asking to decrease wafer capacity, since ARL was a bit of a dud, and maybe they thought ARL wouldn't sell well (and they had to keep prices up there since it's all external, they can't massage the price to sell more).
 

Hitman928

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Is it peak frequency though(They always quote ISO Voltage). A node shrink may or may not have peak frequency improvement.

It’s not really like that and peak frequency is extremely design dependent. It is more that there are improvements that affect frequency, it’s just that the improvements typically work better at “lower” frequencies as more obstacles pop up the higher you go.
 
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Geddagod

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This is not Intel with tons of money they just took a fab write down that same quarter for Billions of $$$ if it was so easy to fab a product everyone would be fabbing a chip.
Except, as I said, you would be spending that money anyway. It's just a matter of spending it like half a year to a year earlier.
You can convert those 20A lines to 18A in the future, and as I said multiple times, you will be gaining that money back since you will be getting better margins from internal. You will be able to launch PTL earlier, and you would be able to have a much more mature 18A node.
BTW, Intel already spent a bunch and invested a bunch into empty fab space too. A lot of the "billions of dollars" in investment have been sunk for a while.
It's unlike the time for Palm Cove with a disabled iGPU on messed up 10nm where they had the money for that botched die.
Very much like that time. In some ways even worse, at least it launched lol, 20A got canned.
They did the financial when Their business was at peak but after COVID their revenue dropped massively but not their investment
Oh I agree, Intel did over estimate during Covid, but then why was 20A cancellation announced so late after that then?
also why is everyone after the 18As lateness? did Intel ever said Products in Q4 24 ? It was H4 24 HVM Readiness
Intel said risk production 2H 24. They announced it 1H 25.
as for cut down performance take a look at their claims they said 10-15% PPW over I3 for 20A and 18A was 5-10% over 20A.
They said 20A would be a 15% perf/watt improvement, and 18A would be 10%.
1753212316012.png
This means 15%-26.5% PPW and last I checked 18% is between those numbers.
Intel only claims 15% for 18A. On the 18A website:
1753212399398.png
Please show me the evidence that 20A was cancelled because of Yield not financial issues.
I've just given you so much.
It wasn't
Intel just tapes out the chips 2 years before launch, so even if Intel were to magically be able to convert N3B physical design to 20A instantly, that's how deep in development 20A ARL variants would have had to be in.
And people are buying more Raptor Lake lol than ARL/LNL combined
ARL and LNL have very little volume, yes.
 

Doug S

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Something only a bit related, but also interesting....

Remember a couple months or a year ago when there were rumors that TSMC increased N3 pricing for Intel specifically by a large amount because of them not liking Gelsinger or something?
I heavily doubted it's validity, since I would imagine the pricing details for the node would have been set long before those rumors started swirling around.
However I wonder if the whole N3 wafer deal was to be renegotiated, which gave TSMC the opportunity to change pricing, and that's also why we had Gelsinger visiting Taiwan (along for securing N2 capacity).

I think there's a couple reasons Intel would have had to try to renegotiate N3B wafers with TSMC:
  • timing, N3B was planned to be used by Intel much earlier than they actually ended up using them. It wasn't simply a quarter or two of a shift. This is the least likely reason though IMO, since it would have been apparent the timeline shift was going to happen much earlier than the "tsmc jacks Intel N3 wafer pricing" rumors started coming.
  • asking to increase wafer capacity, since they no longer had 20A 6+8 tiles planned, and they needed to meet the requirements of the market.
  • asking to decrease wafer capacity, since ARL was a bit of a dud, and maybe they thought ARL wouldn't sell well (and they had to keep prices up there since it's all external, they can't massage the price to sell more).


If Intel didn't get the "known good wafer" pricing for N3B that Apple got, its poor yields compared to N5 family and N3E yields would have acted as an effective price increase for them.
 

Geddagod

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If Intel didn't get the "known good wafer" pricing for N3B that Apple got, its poor yields compared to N5 family and N3E yields would have acted as an effective price increase for them.
A price increase that would have already been factored in, rather than something that changed, which was what was reported.
 
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Io Magnesso

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I wonder why it didn't launch...

You were told by Intel that was the main reason. The other reasons were that they were going to use this to accelerate 18A, which was already on or ahead of schedule (also a lie).
Also, 20A isn't a one off like that investment wise. They very easily could have invested then, and made the production lines pump 18A. 18A is, or sorry, was a sub node improvement over 20A, you prob did not have to change the production line much to make the fabs make 18 rather than 20A. This likely would have accelerated PTL launch too. And they would have recouped a bunch of that money, since Intel whines about how margins have been hit by using TSMC pretty much every earnings call.
The problem is that 20A was very, very likely just unusable. Hence why they had to cut 18A perf/watt claims esentially to the old 20A claims, and why PTL is launching late in the year with only one sku.
Intel 18A is garbage
Nova Lake right now Please make it with TSMC
 

511

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When taken together, from those slides it looks like 18A became 20A, and just kept the name.
Not really 20A would have been a minimalist node just like Intel 4 and 18A would be a superset to 20A like I3 was to I4.
 

511

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When was this?
I remember arguing here on some thread lol have to search myself too many messages found it

 
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dacostafilipe

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Please show me the evidence that 20A was cancelled because of Yield not financial issues.

How can you be so certain that the cancelation was not impacted by yields?

It could be that yield did not increase fast enough on 20A and/or were at the same level as 1618A and it made financial sense to scrap it.
 
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511

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How can you be so certain that the cancelation was not impacted by yields?
I was told by someone reliable that ramping 20A would cost them a tons of $$$ and i am more than willing to believe them 20A may or may not have yield issue but the cost issue is guaranteed just ramping a fab look at TSMC Arizona it is fully booked and yet it incur losses how can you be so sure that Intel wouldn't incur losses on a limited volume node.
It could be that yield did not increase fast enough on 20A and/or were at the same level as 16A and it made financial sense to scrap it.
First there was no 16A lol it is A16 and it is a TSMC process
 
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dacostafilipe

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I was told by someone reliable that ramping 20A would cost them a tons of $$$ and i am more than willing to believe them 20A may or may not have yield issue but the cost issue is guaranteed

So, we are still not certain why it would cost them a ton of money.

First there was no 16A lol it is A16 and it is a TSMC process
Yeah, typo. Should have been 18A :p