Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Io Magnesso]

I forgot there's another way out of Moore's law economic trap for a player like Intel. They can buy ASML, or enough of the upstream drivers of those fixed costs that even if they are a minority player on volume, their fixed costs are subsidized by the majority player. Just runs into a different regulatory hurdle. And it presumes that if they clear that hurdle that the majority player won't buy even more of the upstream drivers as presumably they can clear the same hurdle and have more cash to do so. This is effectively what Apple/Samsung have down by also owning the downstream consumers of the volume because they capture all of the value that the consumer is paying for and can use that as a subsidy.

Moore's Law is not an Economic Trap

It is one indicator that discusses long-term trends in manufacturing and production of large-scale integrated circuits (LSI ICs).
It is a future prediction that is similar to empirical rules.

Separately, each person has a different way of perceiving Moore's law.
It's wrong to think of Moore's law as an economic trap

I'm not saying this to defend Intel.
I'm just trying to disagree because your speech is too rare.
Has Apple Advanced Moore's Law? Please don't be silly It's better to say that
It's still better to argue that the current TSMC is moving Moore's laws forward.

I'm looking forward to seeing what the people involved in the actual semiconductor industry think when they see your claim.

 

[Io Magnesso]

Moore's Law can be said to be the goal of the efforts of the semiconductor industry

 

[Joe NYC]

BTW Zen6 on N2 AND N4C is going to significantly expensive thanks to increasing wafer price TSMC converted N7 fabs to N5 fabs to meet demand.

Is that N4C for IOD or V-Cache? It seems like there will be a whole range of IODs but N4 was mentioned as possible V-Cache Die, since N4 still had a little bit of SRAM scaling.

 

[511]

Is that N4C for IOD or V-Cache? It seems like there will be a whole range of IODs but N4 was mentioned as possible V-Cache Die, since N4 still had a little bit of SRAM scaling.

N4C for IOD if the leaked 155mm2 size is true currently the die is 117mm2 N6. Must be due to co pilot

 

[Joe NYC]

N4C for IOD if the leaked 155mm2 size is true currently the die is 117mm2 N6. Must be due to co pilot

View attachment 127487

Was it a recent leak pointing to 155mm2 IOD on N4C?

 

[511]

Was it a recent leak pointing to 155mm2 IOD on N4C?

It was MLID I don't want to trust him though but @Kepler_L2 said to refer his die size leak so ...

 

[Kepler_L2]

It was MLID I don't want to trust him though but @Kepler_L2 said to refer his die size leak so ...

All of his current AMD diagrams are real.

 

[511]

All of his current AMD diagrams are real.

Bruh need to check looks like Sun rose from the West not East.

 

[del42sa]

https://wccftech.com/smic-5nm-yields-between-60-and-70-percent-claims-tipster/

Latest rumor states that the SMIC’s 5nm yields are in the same range as Samsung’s 3nm GAA technology​

 

[511]

https://wccftech.com/smic-5nm-yields-between-60-and-70-percent-claims-tipster/

Latest rumor states that the SMIC’s 5nm yields are in the same range as Samsung’s 3nm GAA technology​

So the yield sucks?

 

[Doug S]

https://wccftech.com/smic-5nm-yields-between-60-and-70-percent-claims-tipster/

Latest rumor states that the SMIC’s 5nm yields are in the same range as Samsung’s 3nm GAA technology​

I've been predicting for a while they'd be able to get 5nm working, simply based on the fact that TSMC got 7nm working with DUV only at high yields and high production capacity, using DUV machines less advanced than the ones SMIC has. I bet TSMC could have got 5nm working reasonably well DUV only if they had no choice, even with their less advanced DUV. They just didn't have to try.

So SMIC might eventually be able to get 3nm working with their DUV, though even quad patterning may not be enough. Perhaps they can improve on the state of the art for computational lithography though, that would help. Most likely a DUV only 3nm would end up too expensive to go into smartphones, but could be workable for making AI chips or stuff for their defense industry where they would be willing to accept buying more wafers to make up for lower yields.

 

[Geddagod]

So the yield sucks?

Should be at the very least, usable. Something that isn't the case from a bunch of Intel and Samsung nodes in the past lol.

 

[511]

Should be at the very least, usable. Something that isn't the case from a bunch of Intel and Samsung nodes in the past lol.

Remind me which Intel node has faced yield issues except 10nm that was a disaster and has to be the worst disaster in node making should I say. I4/I3 had fine yields

 

[Geddagod]

I'm pretty excited for Exynos 2500 reviews. I don't follow arm stuff that much, but is there some sort of performance embargo on the smartphone or anything? I've seen reviews for the Samsung new phone that uses that chip, but no benchmarks...
And if there is an embargo, anyone know when it will be dropped?
The power curve and die shots should give us a decent idea on where 3GAP, and Samsung 2nm (since Samsung 2nm seems to be a subnode improvement esentially over 3GAP) stand vs TSMC.

 

[Geddagod]

Remind me which Intel node has faced yield issues except 10nm that was a disaster and has to be the worst disaster in node making should I say.

20A.

 

[511]

20A.

Something that didn't launch how can you say it had yield issues I was told the main reason was $$$ they could have ramped it up but it was too much for one off.

 

[Io Magnesso]

20A.

I can't even speculate about the yield of things that haven't been released in the world.
I've never heard of a 20A yield.
I skipped it in the first place

 

[poke01]

hes not wrong and its what others here have been saying

 

[511]

View attachment 127538

hes not wrong and its what others here have been saying

Tolda ya about Mobile not moving to BSPDN soon 😏

 

[Geddagod]

Something that didn't launch how can you say it had yield issues

I wonder why it didn't launch...

I was told the main reason was $$$ they could have ramped it up but it was too much for one off.

You were told by Intel that was the main reason. The other reasons were that they were going to use this to accelerate 18A, which was already on or ahead of schedule (also a lie).
Also, 20A isn't a one off like that investment wise. They very easily could have invested then, and made the production lines pump 18A. 18A is, or sorry, was a sub node improvement over 20A, you prob did not have to change the production line much to make the fabs make 18 rather than 20A. This likely would have accelerated PTL launch too. And they would have recouped a bunch of that money, since Intel whines about how margins have been hit by using TSMC pretty much every earnings call.
The problem is that 20A was very, very likely just unusable. Hence why they had to cut 18A perf/watt claims esentially to the old 20A claims, and why PTL is launching late in the year with only one sku.

 

[jpiniero]

Intel cant afford ASML, but even if they could, it would do nothing for them. Lithography machines 100% do not equal process quality. Everybody uses ASML machines, but Intel has struggled enormously while TSMC has plowed through quite well.

IIRC Intel owned a decent stake in ASML at one point. They sold it though.

 

[511]

I wonder why it didn't launch...

You were told by Intel that was the main reason. The other reasons were that they were going to use this to accelerate 18A, which was already on or ahead of schedule (also a lie).
Also, 20A isn't a one off like that investment wise. They very easily could have invested then, and made the production lines pump 18A. 18A is, or sorry, was a sub node improvement over 20A, you prob did not have to change the production line much to make the fabs make 18 rather than 20A. This likely would have accelerated PTL launch too. And they would have recouped a bunch of that money, since Intel whines about how margins have been hit by using TSMC pretty much every earnings call.
The problem is that 20A was very, very likely just unusable. Hence why they had to cut 18A perf/watt claims esentially to the old 20A claims, and why PTL is launching late in the year with only one sku.

I wasn't told by Intel but an Intel employee or ex Intel employee should I say. It was a big financial issues to ramp that thing.

 

[511]

IIRC Intel owned a decent stake in ASML at one point. They sold it though.

Everyone including TSMC/Samsung had a stake in ASML

 

[oak8292]

I wonder why it didn't launch...

You were told by Intel that was the main reason. The other reasons were that they were going to use this to accelerate 18A, which was already on or ahead of schedule (also a lie).
Also, 20A isn't a one off like that investment wise. They very easily could have invested then, and made the production lines pump 18A. 18A is, or sorry, was a sub node improvement over 20A, you prob did not have to change the production line much to make the fabs make 18 rather than 20A. This likely would have accelerated PTL launch too. And they would have recouped a bunch of that money, since Intel whines about how margins have been hit by using TSMC pretty much every earnings call.
The problem is that 20A was very, very likely just unusable. Hence why they had to cut 18A perf/watt claims esentially to the old 20A claims, and why PTL is launching late in the year with only one sku.

My own take on the five nodes in four years strategy was that the internal only 4 nm and 20A were supposed to be the high frequency relaxed geometry nodes. These were being designed for P core die.

With both 14 nm and 10/7 nm they ‘relaxed’ the geometry for higher frequencies in the performance transistors. Focusing on the performance transistors first and exclusive to Intel would give Intel a competitive advantage even as they provided foundry services.

It seems that neither 4 or 20A met their frequency targets.

 

[511]

My own take on the five nodes in four years strategy was that the internal only 4 nm and 20A were supposed to be the high frequency relaxed geometry nodes. These were being designed for P core die.

With both 14 nm and 10/7 nm they ‘relaxed’ the geometry for higher frequencies in the performance transistors. Focusing on the performance transistors first and exclusive to Intel would give Intel a competitive advantage even as they provided foundry services.

It seems that neither 4 or 20A met their frequency targets.

Well Intel 4 met it's performance target of 20% PPW and 2X Logic Scaling for 20A don't know can or cannot be true cause it was scrapped also nodes have PPA targets not frequency targets,
unless you are cooking up some special flavor like Intel 7 Ultra or N4X/N3X.