Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[ajsdkflsdjfio]

Did you put your life's savings in Intel shares? I mean, taking it a bit personally, aren't you?

Nah 0 dollars invested into intel, and definitely 0 going forward after Pat's departure. I just generally dislike how the most common sentiment, not just in anandtech forums, is to hate on everything intel no matter what. It's reminiscent of anti-AMD culture back in early 2010s and look where that got them.

This is important because this cost needs to be shared by a great number of Intel fab customers over many years to make Intel profitable again. I am concerned that 18A is not "customer friendly" enough to win new designs with as the cost of implementation and production will be prohibitive. Further, unlike TSMC which is opting for a less dense implementation of BSPD with A16 that can support both BSPD and FSPD libraries, Intel is reaping the entire benefit of BSPD in 18A (which is a good thing), but is making it harder for customers to buy into it.

The prevailing thought about BSPD is that it is needed for the next step in process tech (CFET). TSMC may offer their combination BSPD/FSPD nodes clear down to A10 which would then be full BSPD only. When I read this, I thought about just how customer centric and risk adverse this approach really is compared to the more "no-holes-barred" "Regain Process Leadership" approach Intel is using.

I think that by the end of 2025 the story should be much more clear

I agree that TSMC N2 and A16 are likely to be more consumer friendly than 18A. However, I think that the market is good right now for Intel to try and enter the foundry business with TSMC reporting packaging/wafer shortages and TSMC increasing wafer prices not because newer nodes are more expensive but because demand is high, also samsung foundry right now is in the dumps. As you say we'll have a much clearer picture by the end of 2025 since supposedly some of Intel's most major customers start their chip production in 2025.

 

[moinmoin]

It's reminiscent of anti-AMD culture back in early 2010s and look where that got them.

You mean it's actually a good sign for Intel?

 

[ajsdkflsdjfio]

You mean it's actually a good sign for Intel?

Nah, I just mean that overly anti-XYZ company sentiment is foolish and doesn't accurately represent a company's future prospects. Personally I think intel is in a pretty bad spot RN and has been for a while. Even if 18a turns out to be decent (which I think it will), it doesn't mean it will be a commercial success as foundry capacity, process node cost, and whether enough customers will buy into it are still in question. Intel will still need to tread water before foundry turns a profit not to mention their ongoing troubles in their product design, although I'm optimistic for clearwater forest and panther-lake as they'll be on 18a with hopefully better margins and better performance due to being on an Intel node also skymont/darkmont are just generally good. After Pat's removal I'm even less confident in intel but who knows.

 

[KompuKare]

While decades of Intel's hybris makes them a prime target of Schadenfreude, I think the main reason for scepticism with their announcements - especially in foundry - is that for the last decade+ we have seen them be very economical with the truth about claimed milestones, shipments etc. which in the end turned out to be untrue.

Now, we know the story about the boy who cried wolf, but that is no reason to not be sceptical now. Besides 18A has to be more than technically good as foundry is mostly a volume and numbers game.

 

[name99]

AMD granted a glass substrate patent to revolutionize chip packaging — Intel, Samsung, and others racing to deploy the new tech

Originally filed in September, 2021.

www.tomshardware.com

AMD isn't sitting still. Mentions mobile devices. Not confirmed of course but damn if AMD becomes the next Qualcomm

It's Tomshardware. The only speeds they have are "revolutionary" and "minor", both generally incorrect...

It's a stupid statement. Practical effects will be to sustain the pace we are used to - 10..20 percent faster every year at 10..20 percent faster.
Which is nice, but also expected, which is precisely the opposite of "revolutionary"...

 

[name99]

Again, did you read it.

TSMC is recommending it for HPC. I assume this is code for "best suitable for products where the added expense and complexity of advanced cooling methods can be profitably utilized"

Did YOU read it?
High-end (Premium Mobile, Data Center, ...)

Like every process advance TSMC is recommending it for anyone with a bank account that can pay for it.
Which is as it should be, since the tech is generically better, from iPhone next to Blackwell next!

 

[name99]

Lets try again. Intel is coming out with Panther Lake for laptops for next year. At this point, I think it's safe to say both Intel 18A & Panther Lake are not imaginary anymore. They're pretty much real I think regardless of the PR. If Intel's BSPDN is gonna go thermonuclear, then Panther Lake wouldn't exist at all.

And we also know TSMC's BSPDN (SPR) is supposed to be a better implementation than PowerVia. So, all evidence points to this, TSMC's Super Power Rail just can't be as bad as you say it is.

Never a good idea to trust what Intel says.
You should have known better even at the time (ten days ago) because of this:
https://www.reuters.com/technology/...broadcom-tests-disappoint-sources-2024-09-04/
and regardless of exactly how one interprets the firing of Pat G, it certainly doesn't suggest that 18A is ready to roll and make money soon.

There are two issues here that you are merging into one
- is 18A in trouble? Probably.
Is it because of RibbonFET, or PowerVia, or something else? WTF knows? No-one sane trusts anything out of Intel anymore.

- is 16A in trouble? Zero evidence for this, including this weird clickbait hype that takes cautions about "you have to be careful when designing a 1kW chip" (as has ALWAYS been true) and projects that down to phone chips...

 

[name99]

Inspite of smaller SRAM cells, with that kinda heat issue, it's not suitable for most general purpose consumer products (like Zen, Core Ultra, Snapdragon, M series, Nvidia Geforce, etc). TSMC A16 is more of a tech demo. A pipe cleaner. Derisking SPR. In reality, a useless node. It's clear TSMC N2 is going to be their leading node next year.

Yeah yeah yeah.
We've been hearing this sort of claim about various TSMC nodes since at least 20nm. It's always been nonsense so far, but maybe this time...

 

[ajsdkflsdjfio]

Never a good idea to trust what Intel says.
You should have known better even at the time (ten days ago) because of this:
https://www.reuters.com/technology/...broadcom-tests-disappoint-sources-2024-09-04/

https://twitter.com/x/status/1832055416345579629

found in a separate article, also isn't it a given that 18a isn't ready for HVM yet? This "report" was done in q3 2024, when 2H 2025 is 18a's scheduled HVM time.

 

[RTX]

The process guys over at SemiWiki seem to think that BSPD is more expensive than FSPD and that it can require up to 30 deg lower outside temps to achieve the same inside temps for hot spots. Now, I don't know what all that means with respect to which applications will work better than others, but it sure sounds like BSPD has some technical issues that need some solving.

That's just TSMC up charging the AI companies for backside power since they can pass on the costs to their customers.

The prevailing thought about BSPD is that it is needed for the next step in process tech (CFET). TSMC may offer their combination BSPD/FSPD nodes clear down to A10 which would then be full BSPD only. When I read this, I thought about just how customer centric and risk adverse this approach really is compared to the more "no-holes-barred" "Regain Process Leadership" approach Intel is using.

I think that by the end of 2025 the story should be much more clear

It needs both to connect to the top nmos and the bottom pmos in stacked nanowires.

14A should be cheaper/simpler to design than A16.

 

[name99]

Don't you think it will take more fab steps? First you do the power layers and data vias, then the transistors, finishing with the data pathways.

That's the obvious way to do it, but I don't think anyone is doing it that way.
Two alternatives are
- you have two wafers, one built like normal (transistors then signal wiring) and a second that's the power RDL.
Then you mate the two together -- very very accurately...

- the IMEC scheme.
article: https://www.imec-int.com/en/articles/how-power-chips-backside
You build the logic wafer as usual, flip it, remove the silicon (on which the transistors were built) so you have direct access to the transistors, and build your power RDL. (That's simplification, the article gives more details).

I'm pretty sure PowerVia essentially uses the IMEC scheme.
My recollection is that TSMC uses the first scheme I described, but I can't right now find any evidence for that. Maybe I'm misremembering something?

Of course this is more steps! Every new process is more steps, goes with the territory.

 

[name99]

To me it seems more a branding move because TSMC is going to charge a lot more for A16.

Every process costs more than the predecessor. And every time people claim that it's too expensive to be feasible.
You'd think after twenty years of crying wolf they'd have learned something...

 

[name99]

TSMC with competition would have provided BSPD on all of their N2 tier processes without extra cost to its customers. Without competition, TSMC is free to charge even higher price with processes with BSPD.

Better stuff costs more.
This is a boring analysis when applied to iPhones or Macs.
It's equally boring when applied to process nodes.

 

[RTX]

Did YOU read it?
High-end (Premium Mobile, Data Center, ...)

Like every process advance TSMC is recommending it for anyone with a bank account that can pay for it.
Which is as it should be, since the tech is generically better, from iPhone next to Blackwell next!

View attachment 112616

These numbers come with an asterisk next to them for "Datacenter AI products". For mobile, it might be 5% speed, 10% power, 3% chip density.

 

[jpiniero]

Every process costs more than the predecessor. And every time people claim that it's too expensive to be feasible.
You'd think after twenty years of crying wolf they'd have learned something...

There's definitely a breaking point eventually assuming things continue this way. But even if the $/transistor is decently worse on A16, there's going to be products that the power savings will be worth it.

 

[name99]

View attachment 112624
These numbers come with an asterisk next to them for "Datacenter AI products". For mobile, it might be 5% speed, 10% power, 3% chip density.

Apple was already designing SRAMs for a BSDN process in 2022:

US20230299001A1 - Dual Contact and Power Rail for High Performance Standard Cells - Google Patents

A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal...

patents.google.com

I keep trying to point out that BSPDN is not ONLY about reducing resistance in the power network...

 

[OneEng2]

That's the obvious way to do it, but I don't think anyone is doing it that way.
Two alternatives are
- you have two wafers, one built like normal (transistors then signal wiring) and a second that's the power RDL.
Then you mate the two together -- very very accurately...

- the IMEC scheme.
article: https://www.imec-int.com/en/articles/how-power-chips-backside
You build the logic wafer as usual, flip it, remove the silicon (on which the transistors were built) so you have direct access to the transistors, and build your power RDL. (That's simplification, the article gives more details).

I'm pretty sure PowerVia essentially uses the IMEC scheme.
My recollection is that TSMC uses the first scheme I described, but I can't right now find any evidence for that. Maybe I'm misremembering something?

Of course this is more steps! Every new process is more steps, goes with the territory.

Intel's solution is more compact than TSMC's, but doesn't allow for FSPD at all. TSMC's solution gives up some density for process flexibility and also (I believe) is less risky as it is easier to cool and adapt. It is unfortunately more complex (read more expensive) than Intel's PowerVia.

I wouldn't characterize one as better than the other, only different.

 

[Hitman928]

View attachment 112631
Intel's solution is more compact than TSMC's, but doesn't allow for FSPD at all. TSMC's solution gives up some density for process flexibility and also (I believe) is less risky as it is easier to cool and adapt. It is unfortunately more complex (read more expensive) than Intel's PowerVia.

I wouldn't characterize one as better than the other, only different.

This graphic doesn't show TSMC's solution. TSMC's is more advanced than Intel's.

 

[OneEng2]

Nah 0 dollars invested into intel, and definitely 0 going forward after Pat's departure. I just generally dislike how the most common sentiment, not just in anandtech forums, is to hate on everything intel no matter what. It's reminiscent of anti-AMD culture back in early 2010s and look where that got them.

I agree that TSMC N2 and A16 are likely to be more consumer friendly than 18A. However, I think that the market is good right now for Intel to try and enter the foundry business with TSMC reporting packaging/wafer shortages and TSMC increasing wafer prices not because newer nodes are more expensive but because demand is high, also samsung foundry right now is in the dumps. As you say we'll have a much clearer picture by the end of 2025 since supposedly some of Intel's most major customers start their chip production in 2025.

Good point on the market.

This graphic doesn't show TSMC's solution. TSMC's is more advanced than Intel's.

No where near is easy to read as the Intel slide though. In the AnandTech article, it quotes TSMC as saying their solution is more complex though.

 

[RTX]

Same image with the text

 

[FlameTail]

View attachment 112607

4.7 MB/mm² for N2.

 

[FlameTail]

This graphic doesn't show TSMC's solution. TSMC's is more advanced than Intel's.

Is this what you are searching for?

 

[RTX]

Two versions of BPR

 

[dttprofessor]

I generally agree with your sediment.

Intel isn't all bad all the time and in fact, has been outright brilliant on many occasions.

I am increasingly not convinced that 18A is one of them though. Let me elaborate.

I believe that for some applications, 18A will be best-in-class by some margin. It will be almost like the days of old at Intel with a 1 to 2 node advantage for these applications.

The process guys over at SemiWiki seem to think that BSPD is more expensive than FSPD and that it can require up to 30 deg lower outside temps to achieve the same inside temps for hot spots. Now, I don't know what all that means with respect to which applications will work better than others, but it sure sounds like BSPD has some technical issues that need some solving.

A quick search on the estimated cost of 18A to Intel gets a general consensus of around 10 Billion USD. Another 3 Bn and Intel could have bought a brand new Ford class aircraft carrier!

This is important because this cost needs to be shared by a great number of Intel fab customers over many years to make Intel profitable again. I am concerned that 18A is not "customer friendly" enough to win new designs with as the cost of implementation and production will be prohibitive. Further, unlike TSMC which is opting for a less dense implementation of BSPD with A16 that can support both BSPD and FSPD libraries, Intel is reaping the entire benefit of BSPD in 18A (which is a good thing), but is making it harder for customers to buy into it.

The prevailing thought about BSPD is that it is needed for the next step in process tech (CFET). TSMC may offer their combination BSPD/FSPD nodes clear down to A10 which would then be full BSPD only. When I read this, I thought about just how customer centric and risk adverse this approach really is compared to the more "no-holes-barred" "Regain Process Leadership" approach Intel is using.

I think that by the end of 2025 the story should be much more clear

Intel never earn $1 from node,but without lead node,intel never earn $.
Every otherone become brilliant after intel lose the lead node.The lead node is everything for intel, and the nightmare to any otherone.

 

[Hulk]

Naive question coming.

It seems to me that the main advantages to node shrinks are transistor density and a reduction in power. As the costs of these shrinks and time to make them happen have both become enormous for Intel, when does it become economically smarter to leverage the fact that they have foundry capacity with proven older nodes and to just use them?

For example, let's look at Arrow Lake. If Intel could had the foresight to realize 20A would not be ready they could have designed it for Intel 4 or even Intel 7 if necessary. Yes, the dies would have been larger but the yields would have been there from the start (or nearly so) and they would not be paying the additional fee to outsource to TSMC. In addition, their foundry operations would have been fully utilized. The only real downside I see is efficiency, which they obviously don't care that much about anyway and you can make up for that in MT with more cores at lower clocks, yes I understand that is even more die size. My point is that dies on older nodes is the one thing they can do in house economically.

Note that I'm not talking about backports here. I'm saying if they had the foresight to predict where their process would be when the new architecture was taped out. For the last 10 years they have been unable to make this predictions/forecasts and they simply stalled while the competition caught up. Seems like a smart business decision would have been to just "white flag" efficiency and die size (no one really cares anyway how big their die is) and just go for big numbers, good yields in-house on nodes they have under control.

Desperate times call for desperate measures. At the end of the day Dell, HP, and others just need the volume at good prices, +-10% performance doesn't mean anything to most people shopping in Best Buy or corporate buyers, it's about pricing and reliability.