Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Exist50]

Personally I'm more interested in what "being cut down to U level" means, because it implies P dies were used to make some of the U SKUs. (and AFAIK the U SKUs had their own die)

Probably referring to the P dies cut down to 2+8. Those weren't branded as U series, but that's not the kind of detail worth quibbling over.

But I find this logic kind of funny. If Intel launches the small dies first (e.g. TGL), it must be because their yields are so bad they can't make the big ones! And if they launch the bigger die first (ADL), it must be because the yields are so bad they need to have extra cores to cut down! Tails I win; heads you lose!

It's all rather silly, and I thought we were clearly past that by ADL...

 

[Exist50]

IIRC the power usage was meaningfully worse if you got a U that was from the bigger die.

The U die came later because they tried cramming some last minute power saving features in it. It's also a different package.

 

[Exist50]

part of a slide in the Intel Foundry Model Investor WebinarView attachment 82063

This is probably the most honest heads to heads comparison I think I've ever seen from Intel's fabs. It's really only with 18A that they have something worth using. We'll see if they're able to recover.

 

[Exist50]

A public company with a board of directors that is accountable to shareholders doesn’t decide to build a new $30B fab in Germany and another $25B fab in Israel if the existing fab investments are failing to hit it’s existing roadmap.

Yet that's precisely what they're doing, in the hope/assumption that by the time those fabs are done, they're in a good enough position to find customers for them. Even then, we're probably looking more at the next shrink after 18A.

Keep in mind that one of Gelsinger's conditions for taking the roll of CEO is for the board to back his IFS plans. I think at this point the board is along for the ride just as much as anyone else.

 

[H433x0n]

This is probably the most honest heads to heads comparison I think I've ever seen from Intel's fabs. It's really only with 18A that they have something worth using. We'll see if they're able to recover.

Semiwiki, semianalysis and wikichip all disagree with this take.

There’s a vf curve on an industry standard ARM A7 available for both processes, they were even charted.

 

[moinmoin]

One thing I noticed is that if Intel is good at something it's technical marketing.

The product is still planned and the technology used still technically unproven since mass production is still some time off? Nothing to worry about, let's have some forward looking talks at HotChips and the likes with preliminary info, slides, graphs and so on and semi tech sites will eat it up, never mind the fact that it's not in mass production yet.

I feel in the past that's the exact way Intel led itself to keep believing that it's still leader in all possible areas. I just hope it's not deluding itself this time as well.

 

[Geddagod]

One thing I noticed is that if Intel is good at something it's technical marketing.

The product is still planned and the technology used still technically unproven since mass production is still some time off? Nothing to worry about, let's have some forward looking talks at HotChips and the likes with preliminary info, slides, graphs and so on and semi tech sites will eat it up, never mind the fact that it's not in mass production yet.

I feel in the past that's the exact way Intel led itself to keep believing that it's still leader in all possible areas. I just hope it's not deluding itself this time as well.

I'm pretty sure every company does this. All companies project PPA information before launch. TSMC 3nm got delayed, isn't out, and yet we already know PPA estimates and a bunch of the specific measurements and information about the node.

 

[Exist50]

Semiwiki, semianalysis and wikichip all disagree with this take.

There’s a vf curve on an industry standard ARM A7 available for both processes, they were even charted.

Why are you assuming those are both A7 cores? To say nothing of where the data is from...

 

[moinmoin]

I'm pretty sure every company does this. All companies project PPA information before launch. TSMC 3nm got delayed, isn't out, and yet we already know PPA estimates and a bunch of the specific measurements and information about the node.

Of course every foundry company looking for customers does this.

And that's the crucial difference up to now, with Intel having used nodes mostly internally up to now: For Intel customer expectation and planning was no corrective like it is for TSMC (not sure about Samsung, it's been messy enough for a long time now that I'm not sure they have many external customers), with Intel's main customer being itself. This is going to change in a major way once IFS has significant external customers.

 

[maddie]

It’d be insane to move up 20A/18A 6 months from the original timeline released by Gelsinger in 2021 if they’re not hitting targets.

A public company with a board of directors that is accountable to shareholders doesn’t decide to build a new $30B fab in Germany and another $25B fab in Israel if the existing fab investments are failing to hit it’s existing roadmap.

You don’t make those types of business decisions based on wishful thinking.

Try reading about what's happening between China & the US/(West) to see that economics is the least of what's driving this.

 

[coercitiv]

Chipmaker Intel restructures manufacturing business​

Chipmaker Intel restructures manufacturing business

Intel Corp said on Wednesday its manufacturing business will work like a separate unit and will begin to generate a margin, but gave no clear timeline on when it will start scaling up, sending the chipmaker's shares down about 5%.

www.reuters.com

From the article:

Intel's internal business units will now have a customer-supplier relationship with the manufacturing business, Chief Financial Officer David Zinsner said on an investor call. Based on that model, Intel will be the second largest foundry next year with manufacturing revenue of more than $20 billion, he said.

However, the forecast for the business pales in comparison to TSMC sales, which are expected to be close to $85 billion in 2024, said Summit Insights Group analyst Kinngai Chan.

So they're slowly decoupling the foundry business, at least from a financial reporting point of view.

 

[jpiniero]

It’d be insane to move up 20A/18A 6 months from the original timeline released by Gelsinger in 2021 if they’re not hitting targets.

A public company with a board of directors that is accountable to shareholders doesn’t decide to build a new $30B fab in Germany and another $25B fab in Israel if the existing fab investments are failing to hit it’s existing roadmap.

You don’t make those types of business decisions based on wishful thinking.

Part of Pat's job is to convince Shareholders/Pols that everything is awesome. Especially when they are trying to weasel billions from Pols.

Nobody's tried the YOLO strategy before... and if it doesn't work out, then perhaps Intel will just spin off the foundry.

 

[Doug S]

So here's an interesting bit of news. Researchers in Taiwan have figured out a way to speed up the calculations used for computational lithography (i.e. all the fancy calculations necessary to put patterns on masks that will actually result in the patterns they want on the wafer) by 5000x!

I'm not sure exactly how much of today's mask set cost is accounted for by a week or two of number crunching on multiple racks of servers, but this will speed up the process and drop the cost of that component to nearly nothing. Interesting how they accomplished it, too. One of those "seems obvious in hindsight" kind of things that someone had to come up with first (and do the really hard part, actually make it work)

https://techxplore.com/news/2023-06-image-simulation-algorithm-boosts-intensity.html

 

[mderbarimdiger]

Why are you assuming those are both A7 cores? To say nothing of where the data is from...

I wonder why you dismiss the source of the data, the author of that post is IMHO very sensible and worth a read.

 

[Exist50]

I wonder why you dismiss the source of the data, the author of that post is IMHO very sensible and worth a read.

It's completely apples to oranges. We have no particular reason to believe they're even the same core, then you get into silicon results vs simulation, power numbers, N3 vs N3B vs N3E, etc. There's simply no meaningful conclusion one can draw from those scattered points. I think Intel themselves choosing N3 over Intel 3 says far more about how those nodes compare.

 

[Geddagod]

It's completely apples to oranges. We have no particular reason to believe they're even the same core, then you get into silicon results vs simulation, power numbers, N3 vs N3B vs N3E, etc. There's simply no meaningful conclusion one can draw from those scattered points. I think Intel themselves choosing N3 over Intel 3 says far more about how those nodes compare.

David Schor presumed it was an ARM A7 core, which is where the original speculation comes from. It could also be the same Risc-V core they are using in Horse Creek.
This is what Raichu said

For the P127x (pretty sure he is reffering to Intel 4, he quoted his tweet of saying Intel 4 was P1277), they used the x76e testchip which has A53 core, Crypto, GFX, and other parts.

Techinsight scaled using Intel 10nm SF being ~ TSMC N7 in perf for their claim saying Intel 4 will be ahead of TSMC 3nm in perf/watt. If you assume that TSMC N7 is ~ Intel 7, you would still get Intel 3 being at least as high in perf/watt compared to TSMC N3.
Aren't both Intel 4 and TSMC figures silicon results?
I think Intel shifted ARL over from its originally designed node because they saw an opportunity. They couldn't do the same with TSMC, but they had way more flexibility with their internal fabs. It may bite them in the butt depending on how ARL mobile's TSMC 3nm vs Intel 20A timeline occurs, but who knows.

 

[lightisgood]

Techinsight scaled using Intel 10nm SF being ~ TSMC N7 in perf for their claim saying Intel 4 will be ahead of TSMC 3nm in perf/watt. If you assume that TSMC N7 is ~ Intel 7, you would still get Intel 3 being at least as high in perf/watt compared to TSMC N3.

Yesterday, IDM 2.0 was updated.
Intel announced that they deal with internal fabless customers on the same basis as external fabless customers.

So, I guess that majority of ARL family use TSMC N3E instead of selling Intel 3 wafers to NVIDIA (Capacity of Intel 20A would be reduced).

 

[desrever]

If you assume that TSMC N7 is ~ Intel 7,

Intel 7 is nowhere near TSMC N7 in perf/watt, look at how much intel got massacred in perf/watt on mobile side of things.

Alder lake vs Zen3 APUs isn't even a contest, AMD is almost double the perf/watt.



At this point, will Intel 4 even match N7 in perf/watt?

AMD's Chiplets using more power than monilithic die is the only reason Intel is even in the game in performance/watt on desktop.

 

[Exist50]

David Schor presumed it was an ARM A7 core, which is where the original speculation comes from. It could also be the same Risc-V core they are using in Horse Creek.

Or an A53, or anything else. I see no reason to assume it must be the A7.

For the P127x (pretty sure he is reffering to Intel 4, he quoted his tweet of saying Intel 4 was P1277), they used the x76e testchip which has A53 core, Crypto, GFX, and other parts.

p1276.3 = Intel 4
p1276.4 = p1276e = Intel 3
p1277 = Intel 4/3 with PowerVia

Based on the testchip name, hard to tell which node that really corresponds to. But even then, you have best vs typical, and all sorts of ways to present the data.

Techinsight scaled using Intel 10nm SF being ~ TSMC N7 in perf for their claim saying Intel 4 will be ahead of TSMC 3nm in perf/watt. If you assume that TSMC N7 is ~ Intel 7, you would still get Intel 3 being at least as high in perf/watt compared to TSMC N3.

I wouldn't recommend trying to make any meaningful extrapolation from the numbers fabs present. There's no consistency in the comparison points between gens.

Aren't both Intel 4 and TSMC figures silicon results?

I don't think Intel's confirmed the exact origin of that graph.

Intel announced that they deal with internal fabless customers on the same basis as external fabless customers.

Not quite. That's true on an accounting basis, but whether the design teams will be allowed to freely use external nodes will probably be a high (C-suite) level decision. They only used N3 because of desperation.

Alder lake vs Zen3 APUs isn't even a contest, AMD is almost double the perf/watt.

For all that I said above, that's a terrible, meaningless comparison for different nodes. You have 4+8 vs 8+0, different architectures, different power limits, a single narrow workload, etc.

 

[desrever]

For all that I said above, that's a terrible, meaningless comparison for different nodes. You have 4+8 vs 8+0, different architectures, different power limits, a single narrow workload, etc.

Its the best thats available unless you have access to someone fabbing the same chip on both.

Ofc there is architecture differences but both companies are optimizing for similar goals and the results is that. Intel's processors on Intel7 isn't even close to AMD's TSMS N7 parts in performance per watt in both client and server. Unless you think AMD is magically pulling so far ahead of intel on architecture, there has to be a significant difference in the process.

 

[Exist50]

Its the best thats available unless you have access to someone fabbing the same chip on both.

Ofc there is architecture differences but both companies are optimizing for similar goals and the results is that. Intel's processors on Intel7 isn't even close to AMD's TSMS N7 parts in performance per watt in both client and server. Unless you think AMD is magically pulling so far ahead of intel on architecture, there has to be a significant difference in the process.

By the very methodology you used, you'd get radically different efficiencies between a 5600G and a 5800U, despite being the exact same silicon. That's just to highlight the problems with ignoring power limits and core counts, never mind the rest.

 

[desrever]

By the very methodology you used, you'd get radically different efficiencies between a 5600G and a 5800U, despite being the exact same silicon. That's just to highlight the problems with ignoring power limits and core counts, never mind the rest.

Binning matters ofc but its not the focus here, unless you think Intel bins their laptop chips to be higher power just because they want to?

5600G is very efficient as well if you want to compare to intel's desktop CPUs.

 

[Exist50]

Binning matters ofc but its not the focus here, unless you think Intel bins their laptop chips to be higher power just because they want to?

5600G is very efficient as well if you want to compare to intel's desktop CPUs.

This isn't just binning. The same chip with a higher power limit will generally be less efficient at full load. Or the same power limit and less cores. I picked out these two specs just to illustrate where you'd start if you wanted to try to do such a comparison. Throw the architectural and design differences on top, and it's just useless for comparing nodes.

 

[SpudLobby]

Intel 7 is nowhere near TSMC N7 in perf/watt, look at how much intel got massacred in perf/watt on mobile side of things.

Alder lake vs Zen3 APUs isn't even a contest, AMD is almost double the perf/watt.

View attachment 82140

At this point, will Intel 4 even match N7 in perf/watt?

AMD's Chiplets using more power than monilithic die is the only reason Intel is even in the game in performance/watt on desktop.

I'm being blunt but this is the other end of the continuum from H33x or whoever he is. Totally different architectures and different core counts as well. The closest we'd have is the I7 -> i4 Node data with the "Industry Standard Arm Core" but they did not in fact explicitly name that core. Even then it wouldn't be perfect if we didn't know the cache allotments etc, but that would be our best bet to comparing IFS to SS and TSMC. Sadly, again, we don't know what core that was.

 

[SpudLobby]

Semiwiki, semianalysis and wikichip all disagree with this take.

There’s a vf curve on an industry standard ARM A7 available for both processes, they were even charted.

We have no reason to believe it must be an A7 core over an A53. We really don't know. The fact that they weren't even straightforward in the VLSI release about what core it was is telling to begin with - probably because they don't want too many explicit comparisons being done. I doubt that i4 comes out particularly bad relative to say TSMC N5 or Samsung's latest 4NM LPP/LPE, I bet it's in the ballpark - but still. We don't know.