Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[SpudLobby]

VLSI Japan: It’s Better on the Backside

Intel announces its PowerVia technology, and scaling the backside is the next big thing. This could be Intel's moment.

www.fabricatedknowledge.com

Article from somebody who attended VLSI and covers the industry.

IMO, it’s already over and TSMC lost process leadership for HPC. We’re not seeing it yet since the products haven’t released but they will begin trickling out in the next 12 months. I look forward to being mocked over this statement. Does this forum have a “RemindMe” bot?

I feel this is too early. I'll also note Backside Power Delivery is only one thing, one aspect with which Intel can offer clients in pursuit of an advantage or even parity: basic process characteristics a la high volume manufacturing yield, density, power/performance, are still involved. Just having process leadership in terms of "GAAFET + Backside Power Delivery" won't mean much without nailing all the other basics.

We’re not seeing it yet since the products haven’t released but they will begin trickling out in the next 12 months.

So far you'll see Arrow Lake on 20A and besides that there's not much else on 18A that we know of, and Intel would be glad to tell us about ongoing partnerships.

I'm very much cautiously optimistic about Intel, I think they've got a great roadmap going if we take them at their word - they are 2+ years ahead on backside power delivery for example. But I don't think they're that far ahead on GAAFETs, TSMC will produce N2 in 2025, 20A probably has a year on them, 18A probably 6 months assuming all goes well. But based on past results and the whole "high volume manufacturing with proper yields" thing, I think some caution is warranted before we get too optimistic.

I also want to highlight something else about "HPC process leadership". A lot of HPC-class products are actually made on base processes with TSMC or Samsung, e.g. N4, N4P, not N4X, and even AMD for desktop just uses N5. AMD uses N4 for Ryzen mobile chips, Apple uses N5 and N5P for M1 and M2 chips respectively, and even hypothetical and/or future Qualcomm and MediaTek laptop chips or auto chips probably won't use an HPC node, yet TSMC actually classifies those as "HPC" because they are laptop/desktop chips. Graviton 3 is almost certainly on a standard N5 process and not N4X, too. Minimizing leakage and attaining reasonable density still matter beyond smartphones. So it's concerning when we see:

In early 2022, Intel’s foundry arm sent a delegation to Qualcomm’s San Diego headquarters, where they met with CEO Cristiano Amon. Then Intel missed a June performance milestone toward producing those chips commercially. It missed another in December.

Qualcomm executives concluded Intel would struggle making the kind of cellphone chips they wanted, even if it succeeded in making high-performance processors. Qualcomm told Intel it was pausing work while it waits for Intel to show progress, according to people involved in the discussions.

He said Intel has been more focused on chip-making technology that works in high-performance processors like those used in PCs. Making chips for mobile phones with limited battery lives requires new skills and new circuit designs. Intel said recently it is collaborating with Arm, a chip-design company that specializes in cellphone circuits.

They ought to be able to pass this bar, in part because I think HPC is a blurry line and smartphones, laptops, tablets etc still count.

Another thing I want to point out on the note of HPC is discrete GPU's, datacenter or consumer: Nvidia do have a custom process with TSMC. But what's interesting is almost everything we have seen suggest Intel's dedicated GPUs will be fabricated on TSMC processes even through 2026. Certainly today they don't bother with Intel 7.

Anyways, we'll see.

 

[H433x0n]

I feel this is too early. I'll also note Backside Power Delivery is only one thing, one aspect with which Intel can offer clients in pursuit of an advantage or even parity: basic process characteristics a la high volume manufacturing yield, density, power/performance, are still involved. Just having process leadership in terms of "GAAFET + Backside Power Delivery" won't mean much without nailing all the other basics.


So far you'll see Arrow Lake on 20A and besides that there's not much else on 18A that we know of so far, and Intel would be glad to tell us about ongoing partnerships.

I'm very much cautiously optimistic about Intel, I think they've got a great roadmap going if we take them at their word - they are 2+ years ahead on backside power delivery for example. But I don't think they're that far ahead on GAAFETs, TSMC will produce N2 in 2025, 20A probably has a year on them, 18A probably 6 months assuming all goes well.

I think you're off on the TSMC timeline. There won't be any products on TSMC N2 until mid to late 2026 assuming they do not experience any delays on their current road map. The real competitor to 18A is TSMC's N2P and this node isn't projected to be available until 2027 (N2P will be their first node to implement backside power delivery + GAA). All of these timelines are going off of TSMC's published roadmaps, they're referenced in this anandtech article. Their FinFet node with comparable performance to Intel 3 (N3E), will not be available in products until mid next year and is hitting HVM at the same time.

But based on past results and the whole "high volume manufacturing with proper yields" thing, I think some caution is warranted before we get too optimistic.

You know 12 months out from HVM if you have a realistic chance of hitting your target. If 20A/18A were yielding at 10% right now, that timeline would have already been pushed back. The opposite has happened and the road map for 20A/18A has been pushed forward by 6 months from the original estimate given in 2021.

They ought to be able to pass this bar, in part because I think HPC is a blurry line and smartphones, laptops, tablets etc still count.

I think this is a legit concern, but this event you're referencing happened in June 2021 and December 2021. There are some performance characteristics that still need to be ironed out for super low power mobile devices. This has historically always been an issue but it didn't matter as much in the past since the foundry wasn't a pubic facing business. I don't think this will matter too much since 18A HD cells will still have superior low power performance when compared to N3.

 

[Thibsie]

You know 12 months out from HVM if you have a realistic chance of hitting your target. If 20A/18A were yielding at 10% right now, that timeline would have already been pushed back. The opposite has happened and the road map for 20A/18A has been pushed forward by 6 months from the original estimate given in 2021.

No sorry. Intel lied so much about 10nm that nobody should take their words at face value.
They may be honest and they may not be. I sincerely hope they'll do it right this time. They have to prove it.
Until then, those are just words of a convicted liar.

 

[lightisgood]

No sorry. Intel lied so much about 10nm that nobody should take their words at face value.
They may be honest and they may not be. I sincerely hope they'll do it right this time. They have to prove it.
Until then, those are just words of a convicted liar.

Nonsense.
In 2018, we saw Krzanich's Intel.
But now, we see Gelsinger's Intel.

The CEO of Intel holds strong power and many decisions.
This is well-known fact.

 

[SpudLobby]

I think you're off on the TSMC timeline. There won't be any products on TSMC N2 until mid to late 2026 assuming they do not experience any delays on their current road map. The real competitor to 18A is TSMC's N2P and this node isn't projected to be available until 2027 (N2P will be their first node to implement backside power delivery + GAA). All of these timelines are going off of TSMC's published roadmaps, they're referenced in this anandtech article. Their FinFet node with comparable performance to Intel 3 (N3E), will not be available in products until mid next year and is hitting HVM at the same time.

That may be RE: TSMC & 2026. "The real competitor to 18A is TSMC's N2P" Yes, I am aware they are behind overall because of backside power delivery, but keep in mind it's the base process itself where Intel still has so much to prove. Intel 4 doesn't really give us high density libraries, that's Intel 3, and I suspect 20A might follow a similar structure. Intel 4 is quite dense on its HP libraries - I think it looks good - a real N5 competitor, arguably N3 in some aspects. I don't know that Intel 3 will truly compete with N3E in the fashion you think, as much as I would like for that to be the case in part because of FinFlex. Moreover it's rather concerning Qualcomm bowed out already (at least, for now) even on the next generation process. Honestly, it would be pretty encouraging to just see Intel get an Intel 3 client or two, but I assume most are going to just wait for 18A and some backside power delivery.

You know 12 months out from HVM if you have a realistic chance of hitting your target. If 20A/18A were yielding at 10% right now, that timeline would have already been pushed back. The opposite has happened and the road map for 20A/18A has been pushed forward by 6 months from the original estimate given in 2021.

I figured you'd mention that RE: pushed forward, lol. They likely deliberately added some slack in order to present that as it is and demonstrate progress. Intel 4 with Meteor Lake didn't exactly hit the milestones it was supposed to on timing AFAICT, though it wasn't anything crazy, more like a couple quarters. But definitely I don't believe Intel wanted Meteor Lake to be hitting shelves December 31, 2023, which is where we're headed. No, it's not 10NM, but caution warranted.

I think this is a legit concern, but this event you're referencing happened in June 2021 and December 2021. There are some performance characteristics that still need to be ironed out for super low power mobile devices. This has historically always been an issue but it didn't matter as much in the past since the foundry wasn't a pubic facing business. I don't think this will matter too much since 18A HD cells will still have superior low power performance when compared to N3.

So first of all, from the WSJ on the timelines:

In early 2022, Intel’s foundry arm sent a delegation to Qualcomm’s San Diego headquarters, where they met with CEO Cristiano Amon. Then Intel missed a June performance milestone toward producing those chips commercially. It missed another in December.
Qualcomm executives concluded Intel would struggle making the kind of cellphone chips they wanted, even if it succeeded in making high-performance processors. Qualcomm told Intel it was pausing work while it waits for Intel to show progress, according to people involved in the discussions.
He said Intel has been more focused on chip-making technology that works in high-performance processors like those used in PCs. Making chips for mobile phones with limited battery lives requires new skills and new circuit designs. Intel said recently it is collaborating with Arm, a chip-design company that specializes in cellphone circuits.

Is this a typo? I am aware the partnership was first announced in 2021 of course, but this happening in 2022 seems entirely plausible to me based on 18A test chip timelines.

Moving on:

There are some performance characteristics that still need to be ironed out for super low power mobile devices. This has historically always been an issue but it didn't matter as much in the past since the foundry wasn't a pubic facing business.

I agree they'll work on ironing these out - I sure hope they are anyways. I don't think it should be *that* difficult for Intel, presumably much of this revolves around leakage and such, I think they should get there eventually.

I don't think this will matter too much since 18A HD cells will still have superior low power performance when compared to N3.

Well, evidently not on the whole, else we wouldn't be hearing about this from Qualcomm, we know Qualcomm were not interested in Intel 3, which is the only other (save for Intel 16/22FL) Intel Foundry Node, it was 18A they wanted. At any rate, this is an Intel mindset that annoys me: brute forcing like this. You see this even with the mindset about Lunar Lake and (plausibly) using 18A - why the hell can't Intel produce something impressively efficient, performant on Intel 4? That's an architecture and system design vs process distinction (and both matter), but there's a similar lede that gets buried here. I should hope Intel ensures they're juicing every last bit of power and performance they can out of the process, I do think TSMC and Samsung will have competitors and relying on sheer brute force of leads is inefficient.

I'm not negative about Intel per se at all, believe it or not - I hope IFS succeeds (don't care about the design unit as much) but modest skepticism is warranted if only because getting one's hopes up sucks.

 

[DrMrLordX]

and finally shipping Intel 3/4 in volume later this year won't change that. If they can hit schedule with 20A and 18A then I'll believe they've turned things around.

Intel better keep their fingers crossed that they can ship Intel 3 before Q4 2024. Their 20a and 18a schedules are incredibly optimistic as well. There isn't a single foundry out there right now cranking out processes like that. Not TSMC, not Samsung, and certainly not the players who have given up (GF etc.).

 

[Geddagod]

Intel 4 is quite dense on its HP libraries - I think it looks good - a real N5 competitor, arguably N3 in some aspects.

Intel 4's HP density is as dense as N3E? (I'm pretty sure, I doubt it's regular N3) HP libs. I'm fairly certain GLC/RPC use only UHP in their core design, so moving from that to HP is a great step forward IMO. Hopefully we see them adopting AMD's method of using HD cells with a scattering of taller cells throughout the rest of the core in LNC (at least for N3 variants, idk how GAAFET works).

I don't know that Intel 3 will truly compete with N3E in the fashion you think, as much as I would like for that to be the case in part because of FinFlex.

I think it's a great boon, but I do wonder how much Intel just isn't bothering with finflex due to them moving to GAAFET so quickly. And according to Anandtech, GAAFET is more flexible than even Finfet + Finflex

"Ultimately, this technology will bring the flexibility of FinFET-based nodes a little closer to that of nanosheet/GAAFET-based nodes, which are slated to offer adjustable channel widths to get higher performance or reduce power consumption."

Moreover it's rather concerning Qualcomm bowed out already (at least, for now) even on the next generation process.

Seems to me that's the case of Intel not hitting deadlines, not that they planned for 18A to have worse performance than N3

Something I want to mention though is perf/watt. Intel keeps on espousing these great perf/watt gains node over node, even sub node over sub node, but they would need every inch of those gains in order to compete with TSMC at low power.
ICL, and even TGL's low power frequency at the same power versus Zen 3/Zen 2 is just horrific. While I'm sure some of it comes down to design choices, the difference in frequency is just way too large.
For example, according to hwcooling.net, a 4C TGL chip (1165g7) clocks 80% as high as the 5500u in the same blender benchmark @~12 watts, which is especially embarrassing as the 5500u is a 6C chip on zen 2...
At ~17 watts, it's ~85% as high as the 5500u, which again, is still pretty bad considering the 5500u has 50% more cores.
Over at computerbase, we see the 4900hs clocking ~5-10% faster than the 1065g7 at 25 watts, while also having double the cores.

What's actually a little surprising is that ~16 watts, TGL appears to have achieved an ~25% gain in frequency vs ICL.

 

[Doug S]

I think it's a great boon, but I do wonder how much Intel just isn't bothering with finflex due to them moving to GAAFET so quickly. And according to Anandtech, GAAFET is more flexible than even Finfet + Finflex

Perhaps. But this could be at the root of what Qualcomm was talking about in the quotes above. Intel has always been HPC focused (HPC in the meaning of "PCs/servers i.e. the market that wants to maximize transistor switching frequencies" vs "smartphones and embedded devices i.e. the market where power consumption is paramount") while TSMC has become laser focused on the mobile / low power side. Even if GAAFET is "more flexible than even FinFET + Finflex" (can you point to where Anandtech said this? I'm hoping they provide more than just making that claim without detailing why that would be true) you still have to actually support that flexibility in your libraries if foundry customers like Qualcomm or potentially someday Apple are going to be interested.

Intel has always been rolling out processes with a high transistor switching frequency focus rather than a low power focus, because that's what their CPU designers wanted to maximize performance. Operating a foundry is about much more than just having a better process than TSMC (assuming they are able to manage that) and Intel's processes have to not only support customers that don't care about operating at 6 GHz, but also support them with all the IP and tools that allow their customers the maximum possible flexibility in their designs.

In the past Intel has done "low power" by undervolting and underclocking chips crafted in basically the same process they use for their high end frequency monsters. They have never had a process designed from the ground up for low power like TSMC's. Unfortunately for them, the foundry market is almost entirely low power focused, with few potential customers that prioritize maximizing transistor switching frequency (and the two biggest, AMD and Nvidia, are also Intel competitors who likely wouldn't be interested in their services unless Intel spins off the fab business someday) So there's going to be an inevitable tug of war between Intel's biggest customer (itself) and its foundry customers.

That's probably what's up with "Intel 4" versus "Intel 3" and "20A" vs "18A" - first they come out with what their CPU designers want, then they modify it to deliver what their foundry customers (if they had any of note) want. The polar opposite of how TSMC does things with their 'X' variants.

 

[Geddagod]

Perhaps. But this could be at the root of what Qualcomm was talking about in the quotes above. Intel has always been HPC focused (HPC in the meaning of "PCs/servers i.e. the market that wants to maximize transistor switching frequencies" vs "smartphones and embedded devices i.e. the market where power consumption is paramount") while TSMC has become laser focused on the mobile / low power side. Even if GAAFET is "more flexible than even FinFET + Finflex" (can you point to where Anandtech said this? I'm hoping they provide more than just making that claim without detailing why that would be true) you still have to actually support that flexibility in your libraries if foundry customers like Qualcomm or potentially someday Apple are going to be interested.

Intel has always been rolling out processes with a high transistor switching frequency focus rather than a low power focus, because that's what their CPU designers wanted to maximize performance. Operating a foundry is about much more than just having a better process than TSMC (assuming they are able to manage that) and Intel's processes have to not only support customers that don't care about operating at 6 GHz, but also support them with all the IP and tools that allow their customers the maximum possible flexibility in their designs.

In the past Intel has done "low power" by undervolting and underclocking chips crafted in basically the same process they use for their high end frequency monsters. They have never had a process designed from the ground up for low power like TSMC's. Unfortunately for them, the foundry market is almost entirely low power focused, with few potential customers that prioritize maximizing transistor switching frequency (and the two biggest, AMD and Nvidia, are also Intel competitors who likely wouldn't be interested in their services unless Intel spins off the fab business someday) So there's going to be an inevitable tug of war between Intel's biggest customer (itself) and its foundry customers.

That's probably what's up with "Intel 4" versus "Intel 3" and "20A" vs "18A" - first they come out with what their CPU designers want, then they modify it to deliver what their foundry customers (if they had any of note) want. The polar opposite of how TSMC does things with their 'X' variants.

They don't elaborate. Mb I thought I linked it above, but ig I didn't. Here it is. It's the last sentence of the last paragraph in the Finflex section of the article.

 

[RnR_au]

I think you're off on the TSMC timeline. There won't be any products on TSMC N2 until mid to late 2026 assuming they do not experience any delays on their current road map.

The article says 2025....

Today, the company said that N2 technology development is on track and the node will enter high-volume production in 2025 (probably very late 2025).

 

[Doug S]

They don't elaborate. Mb I thought I linked it above, but ig I didn't. Here it is. It's the last sentence of the last paragraph in the Finflex section of the article.

Thanks for the link. The way I read that by saying GAAFET/nanosheet are "slated" to offer adjustable width channels I think they're implying that is something that will can be done eventually, not from day one. I wouldn't necessarily expect Intel's first GAA node to support Finflex like capabilities, like BSPR for TSMC that may come later.

 

[H433x0n]

The article says 2025....

That's for GAAFet with front side power delivery in 2H 2025. That’s not analogous to 18A. The node comparable to 18A would be N2P and that’s on their roadmap for 2026.

I’m not even counting what fabs claim is “high volume manufacturing” as anything real. Technically TSMC had N3 done in 2H 2022 by that metric since they had a press release on December 30th (the final hours of 2H 2022) proclaiming N3 is in high volume production. The reality is we won’t see a CPU/GPU fabbed on N3E silicon until mid next 2024 assuming there are no further delays.

 

[Doug S]

That's for GAAFet with front side power delivery in 2H 2025. That’s not analogous to 18A. The node comparable to 18A would be N2P and that’s on their roadmap for 2026.

I’m not even counting what fabs claim is “high volume manufacturing” as anything real. Technically TSMC had N3 done in 2H 2022 by that metric since they had a press release on December 30th (the final hours of 2H 2022) proclaiming N3 is in high volume production. The reality is we won’t see a CPU/GPU fabbed on N3E silicon until mid next 2024 assuming there are no further delays.

You're just going to ignore the 100 million plus Apple products that will ship with TSMC's N3 before mid 2024?

 

[H433x0n]

You're just going to ignore the 100 million plus Apple products that will ship with TSMC's N3 before mid 2024?

It would be N3B, which would be going backwards costs per transistor so unless TSMC is subsidizing it I’m not sure how that’s going to work. N3B isn’t IP compatible with other N3 nodes so if it’s used it wouldn’t be in anything but A17 processor.

There’s also nothing confirming if that is even happening. There was a statement a few months back that they currently couldn’t meet Apple’s demand for N3.

 

[Doug S]

It would be N3B, which would be going backwards costs per transistor so unless TSMC is subsidizing it I’m not sure how that’s going to work. N3B isn’t IP compatible with other N3 nodes so if it’s used it wouldn’t be in anything but A17 processor.

There’s also nothing confirming if that is even happening. There was a statement a few months back that they currently couldn’t meet Apple’s demand for N3.

So basically you're saying "N3B doesn't count, because reasons". So what if I say Intel 20A doesn't count, because it isn't a foundry node? That's as valid as your tortured logic.

 

[H433x0n]

So basically you're saying "N3B doesn't count, because reasons". So what if I say Intel 20A doesn't count, because it isn't a foundry node? That's as valid as your tortured logic.

I would say that viewpoint has some merit but not because it's not a foundry node (I doubt they wouldn't sell it if they had somebody who wanted it) but because it's not a full node. I take the release of Intel 4 & 20A as essentially a leading-edge indicator that the real thing should be imminent.

That's not me saying it's the wrong move or discounting it but rather acknowledging there's a difference between a node that has a full PDK and associated libraries and nodes that are not yet mature like Intel 4 / TSMC N3B.

 

[Ajay]

Intel inks deal with German Gov't over new FAB:

"Building the 'Silicon Junction' in Magdeburg is a critical part of our strategy for Intel's growth. Combined with last week's announcement of our investment in Wrocław, Poland, and the Ireland sites we already operate at scale, this creates a capacity corridor from wafers to complete packaged products that is unrivaled and a major step toward a balanced and resilient supply chain for Europe," said Intel CEO Pat Gelsinger. "We're grateful to the German federal government, Chancellor Olaf Scholz and the government of Saxony-Anhalt for their partnership and shared commitment to fulfilling the vision of a vibrant, sustainable, leading-edge semiconductor industry in Germany and the EU."

Chancellor Olaf Scholz of Germany said, "Today's agreement is an important step for Germany as a high-tech production location - and for our resilience. Intel's semiconductor production in Magdeburg is the single largest foreign direct investment in German history. With this investment, we are catching up technologically with the world's best and expanding our own capacities for the ecosystem development and production of microchips. This is good news for Magdeburg, for Germany and for all of Europe."

Write up here -> https://www.techpowerup.com/310243/...scope-for-wafer-fabrication-site-in-magdeburg

 

[moinmoin]

Intel inks deal with German Gov't over new FAB:

Write up here -> https://www.techpowerup.com/310243/...scope-for-wafer-fabrication-site-in-magdeburg

The government support reportedly increased from 6.8 to 9.9 billion Euro. Looks like Intel played its cards well there.

 

[H433x0n]

A public source on some of my earlier posts about TSMC's N3 development when responding to Doug S.

“While the high cost of EUV multi-patterning has made the cost/benefit of EUV unattractive, loosening the design rules to minimize the number of EUV multi-patterning layers has led to a much higher die size,” Hosseini said. The “real” 3-nm node will not scale until a higher-throughput EUV system, ASML’s NXE:3800E, is available during the second half of 2023, he added.

The NXE:3800E will help improve wafer throughput by about 30% over the current NXE:3600D by lowering the overall cost of EUV multi-patterning, according to Hosseini.

TSMC will accelerate adoption of the NXE:3800E in the first half of 2024 as the foundry scales N3E and other variations of the 3-nm node for more customers, Hosseini said in the report.

Also:

Apple will pay TSMC for known good die rather than standard wafer prices, at least for the first three to four quarters of the N3 ramp as yields climb to around 70%, Brett Simpson, senior analyst at Arete Research, said in a report provided to EE Times.

The silicon that will be in the iPhone 15 is essentially N4+. It's not a full node jump and it's a cost per transistor regression which is why TSMC will be subsidizing the costs for Apple. It's got 25 layers and significantly decreases wafer throughput.

 

[Doug S]

A public source on some of my earlier posts about TSMC's N3 development when responding to Doug S.


Also:

The silicon that will be in the iPhone 15 is essentially N4+. It's not a full node jump and it's a cost per transistor regression which is why TSMC will be subsidizing the costs for Apple. It's got 25 layers and significantly decreases wafer throughput.

That's a complete lie. N3B is very similar in all performance/density/power metrics to N3E, it is in no way "N4+". That's Intel shill talk.

There may be some yield issues that account for why Apple is paying for KGD versus per wafer. Throughput wouldn't affect a decision about how to pay.

 

[H433x0n]

That's a complete lie. N3B is very similar in all performance/density/power metrics to N3E, it is in no way "N4+". That's Intel shill talk.

There may be some yield issues that account for why Apple is paying for KGD versus per wafer. Throughput wouldn't affect a decision about how to pay.

What do you consider a proper node jump? The jump from N4 to N3 is a 27% density increase (98M/Tr -> 124M/Tr) on its 2-2 fin HP library when comparing like for like. In comparison the jump from N7 HP to N5 HP was >50%. The performance differences between N3B and N3E are negligible, the primary difference is in cost to produce and yields making N3E at least worthy of mass adoption.

None of these numbers are my own, they’re all publicly reported on figures or directly from TSMC themselves.

 

[Thunder 57]

What do you consider a proper node jump? The jump from N4 to N3 is a 27% density increase (98M/Tr -> 124M/Tr) on its 2-2 fin HP library when comparing like for like. In comparison the jump from N7 HP to N5 HP was >50%. The performance differences between N3B and N3E are negligible, the primary difference is in cost to produce and yields making N3E at least worthy of mass adoption.

None of these numbers are my own, they’re all publicly reported on figures or directly from TSMC themselves.

Citation needed.

Even if you are right, it takes no more than a minute or two to include a link. Otherwise people wont believe anything you say like some other forum poster we all joke about.

 

[H433x0n]

Citation needed.

Even if you are right, it takes no more than a minute or two to include a link. Otherwise people wont believe anything you say like some other forum poster we all joke about.

N5 HP Cell: 92.3 MT/mm²
N4 HP Cell: 97.8 MT/mm²
N3 HP Cell: 124.00 MT/mm²

Here's a TSMC graphic that shows N3E with a 30% density improvement over the first version of N5. To say that N3E only brings ~26-27% density improvement over N4 which is 0.94 of original N5 isn't outlandish. There is no sram density improvements, so that ~27% process shrink has to be brute forced through logic scaling.

Edit2: The figures for N5, N4, N3 HP cells are from this article and this article.

 

[Doug S]

View attachment 81971
N5 HP Cell: 92.3 MT/mm²
N4 HP Cell: 97.8 MT/mm²
N3 HP Cell: 124.00 MT/mm²

Here's a TSMC graphic that shows N3E with a 30% density improvement over the first version of N5. To say that N3E only brings ~26-27% density improvement over N4 which is 0.94 of original N5 isn't outlandish. There is no sram density improvements, so that ~27% process shrink has to be brute forced through logic scaling.

Edit2: The figures for N5, N4, N3 HP cells are from this article and this article.

Logic density is scaling by 1.6x. The scaling from N7 to N5 was 1.7x, so basically the same.

You are whining about "chip density" which includes cache which is barely scaling at all anymore. For anyone - that's true for Intel also. GAA & BSPR should help but that's just a short term fix that will only help for a couple generations, cache scaling is going to be a problem everyone faces going forward.

 

[H433x0n]

Logic density is scaling by 1.6x. The scaling from N7 to N5 was 1.7x, so basically the same.

You are whining about "chip density" which includes cache which is barely scaling at all anymore.

It's not basically the same since it's a much less substantial improvement (when factoring in logic + sram), it's going to be a full year behind schedule and they're unable to do it without new equipment. I suppose they could do it, but it'd require 25-26 layers and it is currently yielding at 50% per the EETimes article I linked earlier.

GAA & BSPR should help but that's just a short term fix that will only help for a couple generations, cache scaling is going to be a problem everyone faces going forward.

Everything is a short-term fix in the semiconductor industry. None of these companies are infallible, there are no entrenched leaders in the industry. That's the point I'm trying to get across, I’m trying to dispel the idea that TSMC is a 10 ft tall juggernaut that always executes on time.