Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Geddagod]

That's a complete lie. N3B is very similar in all performance/density/power metrics to N3E, it is in no way "N4+". That's Intel shill talk

N3B has slightly better density than N3E, but sacrifices a bit in power and efficiency. Both are jumps over N4/N5 though, ye.
I agree with the point that, if N3B is considered a 'fake' node because only Apple uses it, then what's the differentiation between that and Intel using their own nodes and being the only customer for their own fabs?

there's a difference between a node that has a full PDK and associated libraries and nodes that are not yet mature like Intel 4 / TSMC N3B.

AFAIK TSMC N3B is going to be in a lot better state than Intel 4- I never heard of N3B only using HD cells or anything of that sort. Sure, only Apple is going to use it, but that's really no different than Intel 4 only being used by Intel (except some very minor other companies- horse creek, that telecom thing, etc etc).

 

[Geddagod]

I haven't seen this mentioned on this forum, but if it has MB...
But anyone notice the 6% peak frequency gain for BSPD is quoted for Intel 4 HP (3 fin) libs versus Intel 4 HD (2 fin) libs?
Wouldn't this mean that the frequency gain iso fin count would be larger than 6%? For 10nm, the difference between HP and HD lib peak frequency was ~5-8%, so the peak frequency gain can be much larger.

 

[Doug S]

I’m trying to dispel the idea that TSMC is a 10 ft tall juggernaut that always executes on time.

No one does. And Intel has been by far the worst at execution in the past decade, but you seem to be assuming that they will deliver everything on time and at mass production volume - you are full of criticism and doubt about TSMC but take everything Intel claims as gospel.

Intel will have the same issues with logic density scaling far better than cache, it isn't like Intel is going to double density from Intel 3 to 20A/18A either.

Personally I would love to see Intel catch up / take leadership and become a major player in the foundry business. Having all our eggs in Taiwan's basket is risky - not only from the "maybe China invades" but a really big earthquake could be just as devastating. But just because it is something I want to see doesn't mean I abandon all reason and decide Intel is going to do it just because they said they would. Intel has lied to us over and over again in the past decade, I need to see some proof before I start believing them again.

 

[Doug S]

I haven't seen this mentioned on this forum, but if it has MB...
But anyone notice the 6% peak frequency gain for BSPD is quoted for Intel 4 HP (3 fin) libs versus Intel 4 HD (2 fin) libs?
Wouldn't this mean that the frequency gain iso fin count would be larger than 6%? For 10nm, the difference between HP and HD lib peak frequency was ~5-8%, so the peak frequency gain can be much larger.

You would think so, but if true wouldn't Intel have called that out themselves given that they're trying to hype BSPD since they will have it first?

 

[igor_kavinski]

You would think so, but if true wouldn't Intel have called that out themselves given that they're trying to hype BSPD since they will have it first?

Keeping their cards close to the chest so they can bulldoze AMD?

 

[H433x0n]

No one does. And Intel has been by far the worst at execution in the past decade, but you seem to be assuming that they will deliver everything on time and at mass production volume - you are full of criticism and doubt about TSMC but take everything Intel claims as gospel.

Intel will have the same issues with logic density scaling far better than cache, it isn't like Intel is going to double density from Intel 3 to 20A/18A either.

Personally I would love to see Intel catch up / take leadership and become a major player in the foundry business. Having all our eggs in Taiwan's basket is risky - not only from the "maybe China invades" but a really big earthquake could be just as devastating. But just because it is something I want to see doesn't mean I abandon all reason and decide Intel is going to do it just because they said they would. Intel has lied to us over and over again in the past decade, I need to see some proof before I start believing them again.

A year ago I would’ve been right there with you. The entire company devolved into a mess during the Krzanich & Swan eras.

Based on all of the external indicators I’m inclined to believe things have changed. There are multiple parallel programs and off-ramps available for the fabs that make me believe the internal culture has changed and it’s not just PowerPoint presentations. If they have Intel 4 yielding decent with BPD (according to their VLSI presentation) then I don’t think Intel 3 is going to turn out an unmitigated disaster like 10nm. I doubt Gelsinger is signing huge fab construction projects with the backdrop of 20A/18A at a defect rate similar to 10nm in 2017/2018; that would be suicidal.

Maybe I’m a pie in the sky naive optimist who knows - it’s possible. This place would be boring if everybody agreed, so I’m happy to play the role as the dissenting voice.

 

[Mopetar]

You would think so, but if true wouldn't Intel have called that out themselves given that they're trying to hype BSPD since they will have it first?

Maybe they've figured out the virtue of keeping their mouths closed until they can deliver on. Maybe at one point they could get by on past success and talk of the marvelous future they had in store, but these days their promises are good for a laugh, and it's really more of a chortle since it's getting a bit sad.

Even if they miss their own mark by a bit, no one will notice they underdelivered on a promise they never actually made. Instead people will be surprised and thrilled to see that Intel might have some gas in the tank for a change.

 

[Geddagod]

A year ago I would’ve been right there with you. The entire company devolved into a mess during the Krzanich & Swan eras.

Based on all of the external indicators I’m inclined to believe things have changed. There are multiple parallel programs and off-ramps available for the fabs that make me believe the internal culture has changed and it’s not just PowerPoint presentations. If they have Intel 4 yielding decent with BPD (according to their VLSI presentation) then I don’t think Intel 3 is going to turn out an unmitigated disaster like 10nm. I doubt Gelsinger is signing huge fab construction projects with the backdrop of 20A/18A at a defect rate similar to 10nm in 2017/2018; that would be suicidal.

Maybe I’m a pie in the sky naive optimist who knows - it’s possible. This place would be boring if everybody agreed, so I’m happy to play the role as the dissenting voice.

They claimed HVM capable yield. While normally that means 0.2-0.1, in some random Linkledln post by an Intel engineer I remember him claiming he was part of the team that brought Intel 7/10mm from some crazy number to 0.4. While I obviously think Intel 7 and Intel 4 ramp actually started at a point much lower than that, I wouldn't be surprised if Intel claims a node is HVM 'ready' at that point- and they actually won't start ramping until it's around the usual range of <0.2.

 

[H433x0n]

They claimed HVM capable yield. While normally that means 0.2-0.1, in some random Linkledln post by an Intel engineer I remember him claiming he was part of the team that brought Intel 7/10mm from some crazy number to 0.4. While I obviously think Intel 7 and Intel 4 ramp actually started at a point much lower than that, I wouldn't be surprised if Intel claims a node is HVM 'ready' at that point- and they actually won't start ramping until it's around the usual range of <0.2.

They would probably roll with a D0=0.3 if history is any indication on 14nm and 10nm.



If you look at the table charting defect density over time this goes all the way back to Q1 21. Given Intel’s historical trend of ~5% improvement per quarter on their processes it wouldn’t surprise me if Intel 4 were at <=0.25 D0.

 

[jpiniero]

They would probably roll with a D0=0.3 if history is any indication on 14nm and 10nm.

Given that yield was so bad, Intel wasn't even "profitable" on 10 nm until the second quarter of Tiger Lake... I wouldn't be so sure.

I think they are YOLOing the nodes. Whether they can make that work... we will see.

 

[Geddagod]

Given that yield was so bad, Intel wasn't even "profitable" on 10 nm until the second quarter of Tiger Lake... I wouldn't be so sure.

source?

 

[jpiniero]

source?

Go read the financial reports. It was like a hundred mill or two a quarter. Now I assume that was mainly depreciation they were eating up compared to what they were getting out of it.

With Meteor Lake, Intel 4 is only like 25% of the chip itself, and they are also going to have Raptor Lake Refresh to sell too. And no desktop either.

 

[H433x0n]

Given that yield was so bad, Intel wasn't even "profitable" on 10 nm until the second quarter of Tiger Lake... I wouldn't be so sure.

I think they are YOLOing the nodes. Whether they can make that work... we will see.

I doubt that.. By 2021 the 10nm node wasn't in as bad of shape. They released Alder Lake only 6 months after Tiger Lake was showing up in laptops.

 

[Geddagod]

I agree that 10nm yield was prob way worse than 0.4 defect density, but 10nm+ and 10nm SF?
The way I see the Intel 10nm series was:
Intel 10nm, cannon lake, completely broken
Intel 10nm+, icelake, according to tech insights changed fin structure but kept same density, bad clocks and bad yields, but not 'broken'
Intel 10nm SF, tiger lake, prob more expensive from adding extra metal layers, decreased density by going to 60nm CPP options for HP/UHP cells (kept 54nm CPP , for HD prob), fixed clocks and yield eventually became acceptable with TGL ramping up 8C variants as well
Intel 7, Alder Lake, From what I hear Intel 7 is notoriously expensive, but yields are great by this point. Idk if Intel 7 added more metal layers...


Tech Insights has Intel 10nm transistor cost as, what looks like, competitive, with foundry 7nm, but I also think this is using Intel 10SF, not Intel 7.

 

[Doug S]

I agree that 10nm yield was prob way worse than 0.4 defect density, but 10nm+ and 10nm SF?
The way I see the Intel 10nm series was:
Intel 10nm, cannon lake, completely broken
Intel 10nm+, icelake, according to tech insights changed fin structure but kept same density, bad clocks and bad yields, but not 'broken'
Intel 10nm SF, tiger lake, prob more expensive from adding extra metal layers, decreased density by going to 60nm CPP options for HP/UHP cells (kept 54nm CPP , for HD prob), fixed clocks and yield eventually became acceptable with TGL ramping up 8C variants as well
Intel 7, Alder Lake, From what I hear Intel 7 is notoriously expensive, but yields are great by this point. Idk if Intel 7 added more metal layers...

View attachment 82028
Tech Insights has Intel 10nm transistor cost as, what looks like, competitive, with foundry 7nm, but I also think this is using Intel 10SF, not Intel 7.

That's three years old, before Intel switched to the Intel 7 / 4 / 3 / 20A / 18A nomenclature. So at the right side of the x axis where they're talking about "i7" they mean what Intel used to call 7nm, which is now their Intel 4 / Intel 3 node. TSMC's N3 numbers can't possibly be accurate either (except maybe for Apple) since this was before they changed direction with N3E.

 

[jpiniero]

I doubt that.. By 2021 the 10nm node wasn't in as bad of shape. They released Alder Lake only 6 months after Tiger Lake was showing up in laptops.

Initially Alder Lake on mobile was low volume... and seemingly even delayed the first shipments of the smaller die because they had so many partially busted chips that were being cut down to the U level.

The difference between 10 nm and Intel 4 and later is that 10 nm had/has a ton of capacity and could just pump out more chips. It's questionable as to how much capacity they have for the newer nodes.

 

[Exist50]

Initially Alder Lake on mobile was low volume... and seemingly even delayed the first shipments of the smaller die because they had so many partially busted chips that were being cut down to the U level.

Source?

 

[jpiniero]

Source?

You'd have to go back to the Alder Lake (?) thread to see the discussion around that.

 

[Exist50]

You'd have to go back to the Alder Lake (?) thread to see the discussion around that.

There were a lot of claims there that ended up being dead wrong. That's far from a compelling argument.

And why would the smallest die be a problem? We saw no problems with the much larger S and P dies. Or Tiger Lake, which had been shipping in millions of units for a year prior...

 

[coercitiv]

And why would the smallest die be a problem?

Personally I'm more interested in what "being cut down to U level" means, because it implies P dies were used to make some of the U SKUs. (and AFAIK the U SKUs had their own die)

 

[jpiniero]

Personally I'm more interested in what "being cut down to U level" means, because it implies P dies were used to make some of the U SKUs. (and AFAIK the U SKUs had their own die)

IIRC the power usage was meaningfully worse if you got a U that was from the bigger die.

 

[jpiniero]

As for the Germany deal, I have to assume that Intel has a lot of outs on it. Up and to including selling the building on the EU's dime.

 

[jerrytttwww]

part of a slide in the Intel Foundry Model Investor Webinar

 

[desrever]

A year ago I would’ve been right there with you. The entire company devolved into a mess during the Krzanich & Swan eras.

Based on all of the external indicators I’m inclined to believe things have changed. There are multiple parallel programs and off-ramps available for the fabs that make me believe the internal culture has changed and it’s not just PowerPoint presentations. If they have Intel 4 yielding decent with BPD (according to their VLSI presentation) then I don’t think Intel 3 is going to turn out an unmitigated disaster like 10nm. I doubt Gelsinger is signing huge fab construction projects with the backdrop of 20A/18A at a defect rate similar to 10nm in 2017/2018; that would be suicidal.

Maybe I’m a pie in the sky naive optimist who knows - it’s possible. This place would be boring if everybody agreed, so I’m happy to play the role as the dissenting voice.

Whats even changed in the last year? Intel has done nothing of great execution except for desktop CPUs. Gelsinger has been nothing but talk but ended up having all his projections delayed anyways.

 

[H433x0n]

Whats even changed in the last year? Intel has done nothing of great execution except for desktop CPUs. Gelsinger has been nothing but talk but ended up having all his projections delayed anyways.

It’d be insane to move up 20A/18A 6 months from the original timeline released by Gelsinger in 2021 if they’re not hitting targets.

A public company with a board of directors that is accountable to shareholders doesn’t decide to build a new $30B fab in Germany and another $25B fab in Israel if the existing fab investments are failing to hit it’s existing roadmap.

You don’t make those types of business decisions based on wishful thinking.