Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[lightisgood]

See I think the slide is misleading. With the Meteor tile being just cores, they could in theory be able to salvage nearly all chips (down to 1+0 if need be) even with crap defect rates. Now will they sell 1+0+2 Meteor, we shall see, but it wouldn't surprise me that the reason Meteor was 'delayed' was because they needed more time to get enough fully enabled dies to even do a paper launch.

The other products mentioned on the slide have a lot of the die... that if there was a defect there, they would have to toss it in the trash can.

I'd like to quote this from the slide.

> "%Yield (normalized to 100mm2area)"

Clearly, this bases industry standard model.
There is not any rhetoric.
Intel 4 is in best condition in last decade.

 

[jpiniero]

Clearly, this bases industry standard model.

The industry standard is to use a specific core, not products themselves.

 

[lightisgood]

The industry standard is to use a specific core, not products themselves.

https://ocw.mit.edu/courses/2-830j-control-of-manufacturing-processes-sma-6303-spring-2008/4aff1e21de13870355ef44dbe71f45c6_lecture10.pdf

 

[Ajay]

https://ocw.mit.edu/courses/2-830j-control-of-manufacturing-processes-sma-6303-spring-2008/4aff1e21de13870355ef44dbe71f45c6_lecture10.pdf

Uhm...

Characterization Vehicles (Test Chips) Hess, ISQED 2003 Tutorial Images removed due to copyright restrictions. Please see Hess, Christopher. "Test Structures for Circuit Yield Assessment and Modeling." IEEE International Symposium on Quality Electronics Design, 2003.

 

[Doug S]

If that's the case, that doesn't necessarily bode well for any of their EUV nodes unless they're taking delivery of a lot more equipment soon. Assuming the Mizuho report was right (and things may have changed since then), Intel might not be taking significant deliveries of EUV equipment until 2025. And some of that was supposed to be High NA EUV equipment.

Plus unless ASML has significantly increased their capacity to produce EUV machines, all the extra N3 capacity TSMC built out for Intel at one of their research fabs had to have eaten into the available supply of EUV equipment.

Didn't I see something recently claiming that TSMC had delayed some of their EUV orders due to the slowdowns in the PC & smartphone markets? If that's the case, Intel would presumably be the beneficiary.

 

[DrMrLordX]

the slide clearly shows the meteor above the skylake

We must be thinking of a different slide then. The slide I was thinking of showed 14nm, 10nm, and Intel 4 yields relative to one another (with no actual numbers and an unknown scale)

What N3B has to do with Intel's 4?

It's an EUV node, just like Intel 4. You can't automatically assume that Intel's switch to EUV is going to drastically improve yield. I cited N3B as being an EUV node with yield problems.

Or heck if you want to get into real yield problems let's talk about Samsung.

Didn't I see something recently claiming that TSMC had delayed some of their EUV orders due to the slowdowns in the PC & smartphone markets? If that's the case, Intel would presumably be the beneficiary.

You may have, and if that is the case than Intel might have been able to scoop up some machines caught in limbo due to mothballed orders.

 

[eek2121]

Let's not loose context here: this is their first node using EUV machines. EUV machines that will carry them till EUV NA machines will step in to be used on 'Intel next ar whatever they call it" process.
Since they don't have infinite number of EUV machines, "4" looking abandoned, having limited production, might not have anything to do with process and everything to do with their plans for 20A and 18A ?
Intel is still catching up now, would not make much sense to bet the farm on TSMC N5 like process in 2024 ?

And surely yields with EUV are great, we already know that from TSMC 5nm that is using it heavily. I think things will only go down once they need multipatterning with EUV.

Think of Intel 4 as an “early access” version of Intel 3. Intel 3 and Intel 4 are similar. So are 20a and 18a. The reason Intel 4 and 20A will be short lived is because they are design compatible. So no, future products won’t be on Intel 4, but you WILL see products on Intel 3.

If that's the case, that doesn't necessarily bode well for any of their EUV nodes unless they're taking delivery of a lot more equipment soon. Assuming the Mizuho report was right (and things may have changed since then), Intel might not be taking significant deliveries of EUV equipment until 2025. And some of that was supposed to be High NA EUV equipment.

Plus unless ASML has significantly increased their capacity to produce EUV machines, all the extra N3 capacity TSMC built out for Intel at one of their research fabs had to have eaten into the available supply of EUV equipment.



I think the question is, are they actually catching up? Seems like people are bending over backwards to make excuses for them despite them having been a recent market leader in silicon manufacturing and how they're absorbing massive amounts of . . . shall we say, outside investment to prop up their foundry business.


N3B's yields are what,55 - 60%? Not amazing. EUV isn't a magic bullet that automatically makes yields better.

Intel disclosed their EUV output capability and projected future capability a year or two ago. While they are capacity constrained, they still have ample capacity for in-house products. They will soon also have enough capacity to handle external products as well.

Let us rest assured -> this is commercial secret, IF Intel is coming up with products and releasing them, things much be getting better for them. But obviuosly they are moving on to 18/20A that also require same machines. So i will reiterate my claim -> product volume might not be due to process being unhealthy and more about R&D and manufacturing concerns.




Impossible to say when all products on market are 7nm, next year will be crucial. But surely if those products they've announced are not wapoware they will be just fine.



What N3B has to do with Intel's 4? Despite all forum warrior blablering, Intel's 4 is more like TSMC N5 and Intel's 3 is N4? Give or take some nm's.
So 1st generation EUV products and not something where TSMC pushed things to run into trouble.

Unless the information I have has changed (not likely), Intel 4 > TSMC N5*. Intel 4 is actually closer to TSMC N3*. Intel 3 is an optimized version of Intel 4.

 

[Ajay]

Unless the information I have has changed (not likely), Intel 4 > TSMC N5*. Intel 4 is actually closer to TSMC N3*. Intel 3 is an optimized version of Intel 4.

Optimized how?

 

[Doug S]

Optimized how?

Similar to how TSMC's N6 was an optimized N7, N4 was an optimized N5.

 

[Doug S]

Another must see video from Geekerwan, this time about Kirin 9000S in Huawei's Mate 60 Pro:

A couple highlights relevant to this forum:

At 4:45 he compares A510 power draw running the same benchmark at the same clock speed in SoCs built on three different processes - TSMC N4, Samsung 4LPE, and SMIC 7nm. TSMC's N4 is the clear leader but SMIC scores a surprise second place with Samsung bringing up the rear. We've wanted a way to compare processes from different foundries, we finally got our wish!

Geekbench 5 is around 1000 for ST and over 4000 for MT - helped by the custom designed (derived from their ARM server cores) dual threaded big cores. That allows it to edge out Gen 1 Snapdragon in the MT test. Not bad for a first effort by Huawei but nothing to make Qualcomm quake in their boots yet.

 

[Doug S]

Interesting video from Asianometry:

Talks about the N3B vs N3E issues - and if he's right this is a problem that will affect everyone equally and get worse in future nodes (i.e. could be a problem for Intel's 18A ambitions)

As well as another path to toward future nodes - using a free electron laser. Makes it sound great - yeah you need a half billion dollar particle accelerator in your fab, but at least it can be shared across multiple lines. If he's correct about the power savings, this might significantly drive down the cost of operating a fab. Of course it is all in the research stage and there may be some major issues found to be standing in the way of putting it into mass production.

But if was China, faced with the prospect of trying to duplicate the current tin droplet method of EUV which would probably take a decade to clone and put into mass production, maybe you put those resources behind free electron lasers instead? That's a technology their scientists already understand, and if they went all-in on it they would stand a good chance of not only catching up to TSMC/Intel but surpassing them.

 

[Ajay]

Interesting video from Asianometry:

Talks about the N3B vs N3E issues - and if he's right this is a problem that will affect everyone equally and get worse in future nodes (i.e. could be a problem for Intel's 18A ambitions)

As well as another path to toward future nodes - using a free electron laser. Makes it sound great - yeah you need a half billion dollar particle accelerator in your fab, but at least it can be shared across multiple lines. If he's correct about the power savings, this might significantly drive down the cost of operating a fab. Of course it is all in the research stage and there may be some major issues found to be standing in the way of putting it into mass production.

But if was China, faced with the prospect of trying to duplicate the current tin droplet method of EUV which would probably take a decade to clone and put into mass production, maybe you put those resources behind free electron lasers instead? That's a technology their scientists already understand, and if they went all-in on it they would stand a good chance of not only catching up to TSMC/Intel but surpassing them.

Watched that last night, good introductory video. Still, really difficult and expensive piece of equipment to develop into something commercially viable. Providing EUV (down to 6nm) for multiple lithographs/steppers will mean more mirrors losses, but the higher total output seems to have the potential to absorb those loses.

Glad there is a second EUV source being developed - it's healthy for the fab ecosystem. Question is, and maybe I missed it, is there a private company that’s able to raise the funds to get this tech to market?

 

[maddie]

Interesting video from Asianometry:

Talks about the N3B vs N3E issues - and if he's right this is a problem that will affect everyone equally and get worse in future nodes (i.e. could be a problem for Intel's 18A ambitions)

As well as another path to toward future nodes - using a free electron laser. Makes it sound great - yeah you need a half billion dollar particle accelerator in your fab, but at least it can be shared across multiple lines. If he's correct about the power savings, this might significantly drive down the cost of operating a fab. Of course it is all in the research stage and there may be some major issues found to be standing in the way of putting it into mass production.

But if was China, faced with the prospect of trying to duplicate the current tin droplet method of EUV which would probably take a decade to clone and put into mass production, maybe you put those resources behind free electron lasers instead? That's a technology their scientists already understand, and if they went all-in on it they would stand a good chance of not only catching up to TSMC/Intel but surpassing them.

Always wondered why this path was not pushed harder before now. Adjustable frequency, multiple outlets simultaneously.

 

[Ajay]

Always wondered why this path was not pushed harder before now. Adjustable frequency, multiple outlets simultaneously.

Stupid forum is putting my response in quotes, except this 🙄

All the attention and funding was on LPP Tin. Too late to the party. But, with LPP EUV shortcomings exposed via real world runs, there is at least room for reconsideration.

 

[maddie]

Stupid forum is putting my response in quotes, except this 🙄

Sorta reopens the race & nullifies the tech squeeze (speaking softly here). Do you agree?

 

[Doug S]

Always wondered why this path was not pushed harder before now. Adjustable frequency, multiple outlets simultaneously.

By the time it became an alternative there had been too much investment in the tech we now have to change course I suppose.

I mean, if say Nikon decided to pursue this path then there's another technology that looks even more promising should they throw out everything they've done and pursue that or let someone else take the risk and figure if they can continue and bring it to market they'll at least have a chance of earning a return on the investment they've already made?

 

[NostaSeronx]

12FDX's launch and Beyond 12FDX roadmap might be shown September 28th, 2023. It might be delayed till March 2024 though as well.

No one got Fab8's roadmap in late August. Hopefully, someone can actually get Fab1's roadmap in late this month. I hate being forced to wait for the new year roadmap.

Also, HLMC should be announcing their own FDSOI roadmap with Simgui. Same-ish with Globalfoundries' FDSOI: 22nm -> 12nm. Potentially, at the GF Chengdu husk 180/130nm side got memoried, while the 22nm/12nm side got HLMC'd. With China FDSOI(22nm&12nm) will be around ~65k wafers per month. NPI group at this appears to be Huali/Huawei, so Huawei is likely to be Tier0 for FDSOI.

 

[Ajay]

Sorta reopens the race & nullifies the tech squeeze (speaking softly here). Do you agree?

Well, the Japanese are unlikely to be selling top shelf semiconductor manufacturing equipment to the Chinese. EUV is EUV. Anyway, I hope can raise the funding to develop this - if there is a profitable business case for the tech - super cool and adds some competition if EUV which I think is important, at the very least.

 

[FlameTail]

Another must see video from Geekerwan, this time about Kirin 9000S in Huawei's Mate 60 Pro:

A couple highlights relevant to this forum:

At 4:45 he compares A510 power draw running the same benchmark at the same clock speed in SoCs built on three different processes - TSMC N4, Samsung 4LPE, and SMIC 7nm. TSMC's N4 is the clear leader but **SMIC scores a surprise second place with Samsung bringing up the rear.** We've wanted a way to compare processes from different foundries, we finally got our wish!

Geekbench 5 is around 1000 for ST and over 4000 for MT - helped by the custom designed (derived from their ARM server cores) dual threaded big cores. That allows it to edge out Gen 1 Snapdragon in the MT test. Not bad for a first effort by Huawei but nothing to make Qualcomm quake in their boots yet.

Just shows how bad Samsung's 4LPX node is.

 

[Doug S]

Just shows how bad Samsung's 4LPX node is.

Yes I was surprised how poorly it compares. I'm sure it couldn't beat TSMC N7 either, likely not Intel 7 either. Not sure how it compares density wise to TSMC's process family but that "4" in its name may be a marketing fantasy in addition to the "LP" lol

If they can't get their foundry back on track we better hope Intel can, or there will effectively be no competition on the leading edge.

 

[SpudLobby]

Yes I was surprised how poorly it compares. I'm sure it couldn't beat TSMC N7 either, likely not Intel 7 either. Not sure how it compares density wise to TSMC's process family but that "4" in its name may be a marketing fantasy in addition to the "LP" lol

If they can't get their foundry back on track we better hope Intel can, or there will effectively be no competition on the leading edge.

Yeah. But the thing is, LPX is just 5NM per TechInsights. And we all knew it couldn’t beat TSMC N6/7 really due to the yields

What I’d like to see — and this will be good — is Tensor G3 on 4NM LPE/LPP (the real 4NM) vs this. In theory an Exynos 2200 (which was on the actual 4NM LPP/LPE) would work but you’d want a recent one, because yields on 4NM have likely improved.

But yeah Samsung is/was a mess. Tensor G3 really should be our best update on the progress. It’s not as good a comparison as like the 8 Gen 1 -> 8 Gen 1+ was when QC went back to TSMC, but it’s the same Arm IP for the largest CPU core and should be good enough to compare vs the 8 Gen 2 & 9200 on N4 and N4P.

 

[FlameTail]

Yes I was surprised how poorly it compares. I'm sure it couldn't beat TSMC N7 either, likely not Intel 7 either. Not sure how it compares density wise to TSMC's process family but that "4" in its name may be a marketing fantasy in addition to the "LP" lol

If they can't get their foundry back on track we better hope Intel can, or there will effectively be no competition on the leading edge.

Well you should know this: 4LPX is a "faux 4nm" node.

What does that mean? It's rumoured that 4LPX was actually 5LPP rebranded. As well all know 5LPE/5LPP is an evolution of 7LPP, not a brand new node.

4LPE was the "true 4nm" node.

4LPX was used by Qualcomm for the Snapdragon 8 Gen 1. According to rumours, 5LPP was rebranded as 4LPX so that they could parade it as a 4nm chip because Mediatek had released the 4nm Dimensoty 9000.

4LPE "the true 4nm" was used by the Exynos 2200.

4LPE had a density of 136 MT/mm² which is similar to N5 (137 MT/mm2).

The TRUTH of TSMC 5nm

Claimed Density vs Reality

www.angstronomics.com

In the end both nodes proved to be trash, with poor yields and horrible power efficiency.

Samsung is now working on 4LPE (SF4E)'s succesors called 4LPP (SF4) and 4LPP+ (SF4P).

 

[SpudLobby]

Well you should know this: 4LPX is a "faux 4nm" node.

What does that mean? It's rumoured that 4LPX was actually 5LPP rebranded. As well all know 5LPE/5LPP is an evolution of 7LPP, not a brand new node.

4LPE was the "true 4nm" node.

4LPX was used by Qualcomm for the Snapdragon 8 Gen 1. According to rumours, 5LPP was rebranded as 4LPX so that they could parade it as a 4nm chip because Mediatek had released the 4nm Dimensoty 9000.

4LPE "the true 4nm" was used by the Exynos 2200.

4LPE had a density of 136 MT/mm² which is similar to N5 (137 MT/mm2).

The TRUTH of TSMC 5nm

Claimed Density vs Reality

www.angstronomics.com

In the end both nodes proved to be trash, with poor yields and horrible power efficiency.

Samsung is now working on 4LPE (SF4E)'s succesors called 4LPP (SF4) and 4LPP+ (SF4P).

View attachment 86409

Exactly.

 

[NostaSeronx]

UMC 14nm has at least 12 customers and UMC expects to finally make revenue on 14nm. No more seeing this in 2024:


However, this has actually been a thing known since 2021. Most of the new customers were having difficulty so we have this:

(Sigma UMC 14FFC revenue share in Q4 2023: 1%!)

This led UMC to "accidentally" showcase their unannounced upcoming 10nm node. Which is lateral stacked nanowires (nanosheets are rounded rectangles, and nanowires are circular/cylinders). This is only primarily disclosed in their research papers/patents/PhD/executive leaks. Development of the nanowire node started in 2018, with an updated structure being shown in 2021.

Which solves "inefficient heat removal finally results in serious serious self heating effect in FinFET" via "valuable information on a better design of SHE-resistant structure" where "profound influence of SHE to the mobility degradation, which should be taken into consideration on the development of 7nm node and beyond." Which 14FFC suffers heavily from SHE-degradation, OD by >0.1V equals a 40% loss in perf.

Most likely, influenced the move to converting FinFETs into LS-cNWs sooner than later at UMC. Possible case for "10nm" is getting a Switch 2 at UMC, official switchclone inbound?
https://www.synopsys.com/dw/emllselector.php?f=Samsung&n=8 <== which wouldn't be hard to beat.

USJC New Fab => 22nm and larger nodes
UMC Singapore New Fab => 22nm and larger nodes
UMC Taiwan Fabs => Transitional to 14nm and smaller, P6. 12A P7/P8 would be 10nm and lower exclusive fabs.

 

[Doug S]

Well you should know this: 4LPX is a "faux 4nm" node.

What does that mean? It's rumoured that 4LPX was actually 5LPP rebranded. As well all know 5LPE/5LPP is an evolution of 7LPP, not a brand new node.

4LPE was the "true 4nm" node.

4LPX was used by Qualcomm for the Snapdragon 8 Gen 1. According to rumours, 5LPP was rebranded as 4LPX so that they could parade it as a 4nm chip because Mediatek had released the 4nm Dimensoty 9000.

4LPE "the true 4nm" was used by the Exynos 2200.

4LPE had a density of 136 MT/mm² which is similar to N5 (137 MT/mm2).

I didn't know there was a "4LPX", I assumed that was your typo, and ignored the difference in my reply. Geekerwan's video claims his comparison is made with 4LPE not 4LPX.