Discussion Intel's past, present and future

[Joe NYC]

Depend on what's on the base tile, Foveros can be either 2.5D or 3D packaging.

The problem is Intel already built extensive Foveros capacity based on their aggressive tile roadmap.
It would be very expensive if they don't use Foveros.

Intel is not helping things by confusing the technology. Normal terminology:
2D = when 2 dies are next to each other
3D = when 2 dies are on top of each other

The confusion comes from what you call the connecting base die, and if you count the connection from connecting base die to other dies. Also, if the base die has active silicon or not.

So, Intel only has had 3D on paper (for about a decade). The first thing that could maybe called 3D is upcoming Clearwater Forrest. Also, some PVC connections, but that's now all discontinued.

 

[511]

Intel is not helping things by confusing the technology. Normal terminology:
2D = when 2 dies are next to each other
3D = when 2 dies are on top of each other

The confusion comes from what you call the connecting base die, and if you count the connection from connecting base die to other dies. Also, if the base die has active silicon or not.

So, Intel only has had 3D on paper (for about a decade). The first thing that could maybe called 3D is upcoming Clearwater Forrest. Also, some PVC connections, but that's now all discontinued.

What about Lakefield first 3D construct they can do 3D construct if you make the interposer have logic it becomes a 3D construct currently the interposer is passive so there is that also MTL/ARL are 2.5D.

 

[Io Magnesso]

What about Lakefield first 3D construct they can do 3D construct if you make the interposer have logic it becomes a 3D construct currently the interposer is passive so there is that also MTL/ARL are 2.5D.

ARL and MTL are 2.5D at first glance.
but Fouros technology itself is classified as 3D Chip Red

 

[Io Magnesso]

Intel is not helping things by confusing the technology. Normal terminology:
2D = when 2 dies are next to each other
3D = when 2 dies are on top of each other

The confusion comes from what you call the connecting base die, and if you count the connection from connecting base die to other dies. Also, if the base die has active silicon or not.

So, Intel only has had 3D on paper (for about a decade). The first thing that could maybe called 3D is upcoming Clearwater Forrest. Also, some PVC connections, but that's now all discontinued.

PVC is a It's 3.5D chip red properly
Even if the PVC becomes EOL, it is a member of 3.5D chip red.

 

[Io Magnesso]

https://twitter.com/x/status/1947166742951960818

 

[Geddagod]

Because 13mm2?

How much of that is cache? How much of that is the core itself? I honestly am not taking that much stock in that figure.
And having a core that wide with presumably large core private caches could mean you can cut out an enter layer of cache, like what Apple and Qualcomm do.

You can't rely on Vmin so much. At certain voltage levels the frequency plummets. When CPUs were 3.3V, yes they had scaling room.

You start at ~0.6V for when the transistors are barely on and about 1.2V you need to be full bore. How much scaling do you think exists there? This 1990's thinking. At 0.6V it might run at Pentium II speeds, and at 0.95V you are at 4GHz+.

What? Why can't you "rely" on Vmin?
Frequency doesn't "plummet", running at Vmin esentially is going to be the most efficient point in your CPU v/f curve.

 

[511]

How much of that is cache? How much of that is the core itself? I honestly am not taking that much stock in that figure.
And having a core that wide with presumably large core private caches could mean you can cut out an enter layer of cache, like what Apple and Qualcomm do.

What? Why can't you "rely" on Vmin?
Frequency doesn't "plummet", running at Vmin esentially is going to be the most efficient point in your CPU v/f curve.

Even if you take Core+L2 of Royal to be 13mm2 and LNC+L2 is roughly 4.5ish mm2 that still ~2.9X the area for like 40% ST.

Vmin is not necessarily the most efficient point it's the point with the lowest Voltage not the best PPW.

 

[Geddagod]

Even if you take Core+L2 of Royal to be 13mm2 and LNC+L2 is roughly 4.5ish mm2 that still ~2.9X the area for like 40% ST.

That would be Core+L2. L2 is usually counted as part of the core.
So not only is area the easily most changeable aspect of a core, based on physical design, but that version of royal core wasn't even the one that was going to be productized...

Vmin is not necessarily the most efficient point it's the point with the lowest Voltage not the best PPW.

No, it is the point where the core has best perf/watt.

 

[511]

That would be Core+L2. L2 is usually counted as part of the core.
So not only is area the easily most changeable aspect of a core, based on physical design, but that version of royal core wasn't even the one that was going to be productized...

No, it is the point where the core has best perf/watt.

This tells us otherwise

 

[Geddagod]

This tells us otherwise
View attachment 127494

What about this tells us otherwise?
Let's look at perf/watt at each frequency for the Intel 3 curve.
at 3 GHz, total power is ~1, so perf/power ratio is 3.
At 4 GHz, total power is ~1.5 (slightly higher actually), so the perf/power ratio is now 2.7.
At 5 GHz total power is now 4.5. Perf/power ratio is now almost 1.

The higher up you go on the curve, the worse perf/watt is.

 

[Doug S]

When I asked Grok to compare costs of TSMC CoWoS and InFO, Grok estimate is CoWoS is 7x cost of InFO. And as I said, the Foveros technology Intel is using most closely resembles CoWoS.

Seriously? You might as well be asking your magic 8 ball for what it thinks!

If you want to provide information anyone here will actually believe, and you want to use an AI (and why in the world would you use Grok out of all of them?) ask it to provide a LINK that compares the cost. Because Grok has absolutely ZERO f-ing idea what the cost differential is unless it ingested some article somewhere where someone who actually knows made a claim that the cost is 7x higher.

 

[Joe NYC]

Seriously? You might as well be asking your magic 8 ball for what it thinks!

Instead of mocking, you can post a counter argument.

If the information was readily available, there would be no need to ask AI to deduce it. Since the info is not readily available, you can choose to be completely in the dark or you can ask one of the AI tools, to find tidbits of information and then try to connect them.

If you want to provide information anyone here will actually believe, and you want to use an AI (and why in the world would you use Grok out of all of them?)

Because it is the best of the ones I have available.

Google generally generates garbage
CoPilot is very fast, but superficial (gave 4x to 15x range but mixed-up the units)
Grok can do deep search and deep reasoning

ask it to provide a LINK that compares the cost. Because Grok has absolutely ZERO f-ing idea what the cost differential is unless it ingested some article somewhere where someone who actually knows made a claim that the cost is 7x higher.

It seems like you don't have experience in how the LLMs work. They can find credible tidbits and then they can try to find corroborating information.

Google came up with NADA:
"While precise cost per mm² figures are difficult to obtain due to the proprietary nature of these technologies and varying product specifics, the cost difference between the two is significant."
You can read significant as you wish

CoPilot

Relative Cost per mm² (Estimates)​

• CoWoS: Typically ranges from $2,000 to $3,000 per mm².
• InFO: Generally falls between $200 to $500 per mm²

I think this may be per wafer. But pretty good and informative for extremely fast turnaround.

Grok was the only one to be able to find one single reference there is on internet and found out it is relevant:
"One historical account notes that early CoWoS pricing was around 7 cents per mm², which customers deemed too expensive for adoption; they indicated willingness to use it only at around 1 cent per mm². This feedback directly led TSMC to develop InFO as a more cost-effective alternative, achieving broader adoption (e.g., in Apple processors) and generating substantial revenue."

It links to this article:

Behind the Rise of Taiwan Semiconductor's CoWoS: Once Sat on the Bench for 10 Years

台積電 CoWoS 技術由於人工智能的推動而變得火紅。然而，十多年前該技術卻沒有客户，只有賽靈思 (Xilinx) 願意採用。當時每個月只需生產 50 片，數量相當有限。台積電投資了大量資源發展這項技術，但卻沒有收益。最終，他們採取了降低成本的另一種先進封裝技術 InFO。InFO 成為蘋果等智能手機芯片客户採用的先進封裝技術，也是台積電的主要技術之一。

longportapp.com

"Shang-Yi Chiang shared that he had promoted the CoWoS technology to customers everywhere, but no one was willing to use it. Later, during a dinner with a vice president of a customer, the reason for not adopting CoWoS was casually mentioned as the high price. If selling at 7 cents per square millimeter was too expensive, they would only consider using it if it was sold at 1 cent per square millimeter. This realization prompted him to immediately instruct the R&D manager to develop a cost-reducing technology, which turned out to be another advanced packaging technology called InFO."

Grok gave 67 links to web pages on which it based further analysis. And based on those, it gave final estimate as a range of 3x-7x cost differential between CoWoS and InFO.

Downside is that the current deployment level of Grok 4 I have access to is quite slow. Which is why I use CoPilot for simple quick searches.

I invite you to do better than this.

 

[Joe NYC]

What about Lakefield first 3D construct they can do 3D construct if you make the interposer have logic it becomes a 3D construct currently the interposer is passive so there is that also MTL/ARL are 2.5D.

True. The terminology is not clear cut. But it is really stretching it to call 3D when a chip sits on top of interposer or passive base die

 

[Kepler_L2]

True. The terminology is not clear cut. But it is really stretching it to call 3D when a chip sits on top of interposer or passive base die

Pretty standard terminology:

2D = Chip-to-chip on substrate (e.g. Granite Ridge)
2.5D = Chip-to-chip on Passive Interposer or Bridge (e.g. Navi31)
3D = Chip-to-chip on Active Interposer (e.g MI300) or Chip-on-Chip (e.g Ryzen 3D V-Cache)

 

[QuickyDuck]

Pretty standard terminology:

2D = Chip-to-chip on substrate (e.g. Granite Ridge)
2.5D = Chip-to-chip on Passive Interposer or Bridge (e.g. Navi31)
3D = Chip-to-chip on Active Interposer (e.g MI300) or Chip-on-Chip (e.g Ryzen 3D V-Cache)

Well...
AMD says MI300 is 3.5D

 

[Kepler_L2]

Well...
AMD says MI300 is 3.5D

Yeah because it's both 2.5D and 3D (don't ask why 2.5 + 3 = 3.5)

 

[igor_kavinski]

How is that acceptable to engineers?

 

[igor_kavinski]

Well...
AMD says MI300 is 3.5D

How is that acceptable to engineers?

 

[jpiniero]

I want 4D. Goes back in time to calculate the results.

 

[511]

I want 4D. Goes back in time to calculate the results.

why go back in time when you can go to future and fetch the result 10 years from now

 

[Doug S]

Instead of mocking, you can post a counter argument.

If the information was readily available, there would be no need to ask AI to deduce it. Since the info is not readily available, you can choose to be completely in the dark or you can ask one of the AI tools, to find tidbits of information and then try to connect them.




Because it is the best of the ones I have available.

Google generally generates garbage
CoPilot is very fast, but superficial (gave 4x to 15x range but mixed-up the units)
Grok can do deep search and deep reasoning



It seems like you don't have experience in how the LLMs work. They can find credible tidbits and then they can try to find corroborating information.

Google came up with NADA:
"While precise cost per mm² figures are difficult to obtain due to the proprietary nature of these technologies and varying product specifics, the cost difference between the two is significant."
You can read significant as you wish

CoPilot

Relative Cost per mm² (Estimates)​

• CoWoS: Typically ranges from $2,000 to $3,000 per mm².
• InFO: Generally falls between $200 to $500 per mm²

I think this may be per wafer. But pretty good and informative for extremely fast turnaround.

Grok was the only one to be able to find one single reference there is on internet and found out it is relevant:
"One historical account notes that early CoWoS pricing was around 7 cents per mm², which customers deemed too expensive for adoption; they indicated willingness to use it only at around 1 cent per mm². This feedback directly led TSMC to develop InFO as a more cost-effective alternative, achieving broader adoption (e.g., in Apple processors) and generating substantial revenue."

It links to this article:

Behind the Rise of Taiwan Semiconductor's CoWoS: Once Sat on the Bench for 10 Years

台積電 CoWoS 技術由於人工智能的推動而變得火紅。然而，十多年前該技術卻沒有客户，只有賽靈思 (Xilinx) 願意採用。當時每個月只需生產 50 片，數量相當有限。台積電投資了大量資源發展這項技術，但卻沒有收益。最終，他們採取了降低成本的另一種先進封裝技術 InFO。InFO 成為蘋果等智能手機芯片客户採用的先進封裝技術，也是台積電的主要技術之一。

longportapp.com

"Shang-Yi Chiang shared that he had promoted the CoWoS technology to customers everywhere, but no one was willing to use it. Later, during a dinner with a vice president of a customer, the reason for not adopting CoWoS was casually mentioned as the high price. If selling at 7 cents per square millimeter was too expensive, they would only consider using it if it was sold at 1 cent per square millimeter. This realization prompted him to immediately instruct the R&D manager to develop a cost-reducing technology, which turned out to be another advanced packaging technology called InFO."

Grok gave 67 links to web pages on which it based further analysis. And based on those, it gave final estimate as a range of 3x-7x cost differential between CoWoS and InFO.

Downside is that the current deployment level of Grok 4 I have access to is quite slow. Which is why I use CoPilot for simple quick searches.

I invite you to do better than this.

OK so TLDR what Grok did was find a web page that addressed that very issue. Grok didn't "reason", rather it apparently did a better job of searching the web than Google's AI did (which is kinda sad for Google given that search is their bread and butter)

Rather than claiming "Grok told me this" without context and expecting us to take it at face value, if you had simply said "Grok pointed me to this article claiming CoWoS is around 7x more expensive" then people are going to trust that far more. Because you may think you have "experience" in how LLMs work, but if you believe ridiculous claims that LLMs have reasoning abilities you clearly don't have any idea how they actually work. AI could never answer a question like that without finding a link to a human provided answer. Maybe someday we'll have one that can, but I highly doubt LLMs will be a part of the mechanism that gets us there. It is better than what came before, but it is not able to reason.

 

[igor_kavinski]

but it is not able to reason.

Double slit experiment question.

I can't get a straight answer from Chatgpt on this one. Imagine the following double slit experiment. A stream of photos is sent across one of the slits but the detector is located 1 light minute away. So you will not know which slit the electron passed through for 1 minute. Send one electron...

forums.anandtech.com

Is that not reasoning (the Gemini and Grok ones)?

 

[Io Magnesso]

It is kind of curious that no one is talking about the packaging Intel chose for ALL of its current and future products. Because if it is sub-optimal, it would mean admitting all of Intel's products have an Achiles Heel.

When I asked Grok to compare costs of TSMC CoWoS and InFO, Grok estimate is CoWoS is 7x cost of InFO. And as I said, the Foveros technology Intel is using most closely resembles CoWoS.



Let's say on high performance chips (server, high end desktop), AMD may currently have 10% lead, and by 2028, there will be 2 generations, and suppose each one widens the gap by 10%. Which would be 33% overall.

In Gaming, AMD is starting with much wider gap, as much as 30% vs. Arrow Lake.

To be honest, I don't know the cost structure of FOVEROS Because there is little information

 

[oak8292]

OK so TLDR what Grok did was find a web page that addressed that very issue. Grok didn't "reason", rather it apparently did a better job of searching the web than Google's AI did (which is kinda sad for Google given that search is their bread and butter)

Rather than claiming "Grok told me this" without context and expecting us to take it at face value, if you had simply said "Grok pointed me to this article claiming CoWoS is around 7x more expensive" then people are going to trust that far more. Because you may think you have "experience" in how LLMs work, but if you believe ridiculous claims that LLMs have reasoning abilities you clearly don't have any idea how they actually work. AI could never answer a question like that without finding a link to a human provided answer. Maybe someday we'll have one that can, but I highly doubt LLMs will be a part of the mechanism that gets us there. It is better than what came before, but it is not able to reason.

I think I may still go with Google over Grok. Grok has an ‘answer’ but the link is anecdotal and fairly old. If you are just settling an argument that one is more expensive than the other it could be useful. I think relative pricing is beyond anything that is publicly available or what I would believe from Grok.

Apple did not need CoWoS for their packages and I have no doubt the solution they use is less expensive than a silicon substrate.

Apple Ultra with thousands of connections but only between two die uses something like Intel’s EMIB, called InFO-LSI.

TSMC Clarifies Apple's UltraFusion Chip-to-Chip Interconnect

InFO_LI, not CoWoS, says TSMC.

www.tomshardware.com

With multiple HBM and a GPU or CPU with thousands of connections it seems that an ‘expensive’ substrate is the most cost effective.

What is the price per connection in each of these technologies?

 

[DavidC1]

Is that not reasoning (the Gemini and Grok ones)?

It can't reason. It may look like reasoning, because it compiled so much data and correlates between the two.

And it sucks especially when accuracy is required. I'm convinced a big reason for such low accuracy is because the heart of the operation is the GPU and it uses ultra low precision 8 and 16 bit FP compute to do it.

@Joe NYC In addition to that they hallucinate. That's the real problem. Also personally I ignore AI search result at the top because it's been shown the reliance on it decreases our capacity. We aren't saying to completely ignore the results. We're asking you to give actual links too.

I'm reminded of a show in Outer Limits where the character wishes to be a top player in basketball to a genie. The genie fulfills his wish by making all other players retarded. AI can "replace" such humans for sure.