Question Intel's new x86 instruction sets: APX and AVX10

[Gideon]

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

Intel is extending its instruction set. "Intel® APX doubles the number of general-purpose registers (GPRs) from 16 to 32. This allows the compiler to keep more values in registers; as a result, APX-compiled code contains 10% fewer loads and more than 20% fewer stores than the same code compiled for an Intel® 64 baseline.2 Register accesses are not only faster, but they also consume significantly less dynamic power than complex load and store operations."

And AVX10 techincal paper (PDF)

https://cdrdv2.intel.com/v1/dl/getContent/784343

Intel AVX10 includes all the capabilities and features of the Intel AVX-512 ISA, both for processors that feature 256-bit maximum vector register sizes, as well as for processors thatfeature 512-bit vector registers.

Both seem to be a pretty sizable deal.

 

[soresu]

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

And AVX10 techincal paper (PDF)

https://cdrdv2.intel.com/v1/dl/getContent/784343

Both seem to be a pretty sizable deal.

AVX10 sounds a bit like ARM's ARGON/SVE instruction set.

Supports both 256 and 512 bit, but the latter is optional which gives Intel freedom to bring back AVX512 on their P cores after they shot themselves in the foot by not introducing this back with ADL and kicking their vector performance in the nuts.

ie it's more sizable in that it corrects a sizable mistake in their x86 bigLittle planning.

 

[JoeRambo]

"Compiler enabling is straightforward – a new REX2 prefix provides uniform access to the new registers across the legacy integer instruction set. Intel® AVX instructions gain access via new bits defined in the existing EVEX prefix. In addition, legacy integer instructions now can also use EVEX to encode a dedicated destination register operand – turning them into three-operand instructions and reducing the need for extra register move instructions. While the new prefixes increase average instruction length, there are 10% fewer instructions in APX-compiled code2, resulting in similar code density as before."

BIG stuff right there. 3 operand instructions? Straightforward extension by new prefix and extending EVEX? Wow

 

[Abwx]

BIG stuff right there. 3 operand instructions? Straightforward extension by new prefix and extending EVEX? Wow

Seems that they took something from the ARM book...

 

[JoeRambo]

Seems that they took something from the ARM book...

Yeah, a lot of it looks like stright from ARMs 64bit set (not the stupid things they had on v7). 3 operands, conditionals, vector flexibility stuff, more registers and probably other ARM like things.

What they did not take it seems is "variable" register length that noone is actually using on ARM. Quite sensible imo.
And making ALL AVX512 instruction available to operate on 256bit registers is the move they should have made already.

 

[moinmoin]

AVX10 is what should have gone into ADL. All in all all steps into the right directions. Now I just wonder how long they all take before appearing in purchasable products.

 

[mikk]

AVX10 support is coming with Meteor Lake or Arrow Lake?

 

[JoeRambo]

AVX10 is what should have gone into ADL. All in all all steps into the right directions. Now I just wonder how long they all take before appearing in purchasable products.

The main pain point seems to be the fact that small cores will still won't support 512bit vectors. AMD did it the right way with 512bit width, but 256bit execution.
What you get instead is basically "version based" enumeration of capability. Code compiled for those "optional 512bit" registers will run just on Xeon P cores. So average Joe developers will continue to ignore it, but they will get all goodies of AVX512 instruction set everywhere. And i have long been saying on these forums that 512bits width is stupidity from era where GPUs were not order of magnitude faster in workload than these 512bit dual FMA dinosaurs where supposed to run.

Still these new extensions are the right thing for x64 arch, looking forward to first CPUs supporting it.

 

[soresu]

BIG stuff right there. 3 operand instructions?

😅

 

[Saylick]

AVX10 is what should have gone into ADL. All in all all steps into the right directions. Now I just wonder how long they all take before appearing in purchasable products.

AVX10 support is coming with Meteor Lake or Arrow Lake?

Someone on Twitter suggested that Granite Rapids would support it, which I think corresponds to Arrow Lake on the client side.

EDIT: Here we go.


Looks like we don't get AVX10.2 until the product after, though. Granite Rapids will be a transitionary step, so my guess is we don't get AVX10.2 until 2025 at the earliest.

EDIT2: Looks like I jumped the gun earlier. AVX10.1 is for Xeon P-cores only in the form of Granite Rapids. Given that it is AVX10.2 that supports P and E-cores, I now suspect that's the form we'll see it in the client space. Given that Granite Rapids and Arrow Lake are both 2024 products, AVX10 in any form likely won't show up in the client space until 2025?

 

[NostaSeronx]

By the time this comes out to be affordable or at AMD. I would probably be looking at RISC-V. Since, SiFive and/or Tenstorrent and whoever else is making cores. Will definitely be faster than the Sophon SG2042/Etc VisionFire2 now to when APX/AVX10.2 is in production products at Intel or AMD.

 

[soresu]

By the time this comes out to be affordable or at AMD. I would probably be looking at RISC-V. Since, SiFive and/or Tenstorrent and whoever else is making cores. Will definitely be faster than the Sophon SG2042/Etc VisionFire2 now to when APX/AVX10.2 is in production products at Intel or AMD.

HW availability is less important than software support in that case.

Even with Apple pushing an ARM based Mac platform and some degree of forewarning it's taken some time for the big bois in DCC like Adobe, Autodesk etc to migrate their software packages to it.

I don't expect anything like that level of support for RISC-V for a very long time.

 

[NostaSeronx]

HW availability is less important than software support in that case.

Even with Apple pushing an ARM based Mac platform and some degree of forewarning it's taken some time for the big bois in DCC like Adobe, Autodesk etc to migrate their software packages to it.

I don't expect anything like that level of support for RISC-V for a very long time.

Since, GIMP/Inkscape/Blender already supports Apple's chips. It won't take that long for RISC-V chips to get support as well.

Speed of adoption from this:

Rise: RISC-V Software Ecosystem – Linux Foundation Project

riseproject.dev

Is probably going to be faster than adoption of APX/AVX10 in Adobe Photoshop/Illustrator/Maya/etc.

Then, there is the ISA ability of that core in the SG2042/post-TH1520, being the same as XT910. 1024-bit vectors with 256-bit(2x128-bit) units, everyone will have to design against this if it is most adopted. AVX10-series still doesn't have that 11 setting on L',L for 1024-bit.

Anything software can probably be catched by "premium" emulators as hardware becomes more available: https://box86.org/2023/05/box64-and-risc-v/
More proprietary stuff will probably be dependent on how fast Qualcomm gets a developer platform out. Since, if it is openly available to others it is going to get patched in whenever: https://github.com/dotnet/runtime/issues/36748 (progress starts accelerating in 2023) // Qualcomm (CVs/webarchive) :: "for the custom RISC-V CPU" -> "for Nuvia custom CPU" of which Windows on ARM emulator dot com guy is at Qualcomm for some reason.

As well as none of the what Intel is actually doing is what needs to be fixed:

• x86-64 code is not denser than AArch64/RV64 code.
• x86-64 instructions do not perform more work than AArch64/RV64 instructions.
• x86-64 instructions are not shorter than AArch64/RV64 instructions.

 

[A///]

it is as if someone here who kept harping on Intel being able to pull this off weeks ago knew something big was coming along all along. Cheers lads. hmmmmmmmmmmmmm

and for the few who cared, i was well after my last post. no evil cardiac events.

 

[TheELF]

after they shot themselves in the foot by not introducing this back with ADL and kicking their vector performance in the nuts.

ie it's more sizable in that it corrects a sizable mistake in their x86 bigLittle planning.

They made great sales with the old hybrid CPUs and now the same people that bought the old hybrids are going to buy the new ones.
They shot the consumers in the foot not themselves.

 

[coercitiv]

They shot the consumers in the foot not themselves.

This line of thinking right here is the reason Intel is facing it's worst struggle in history.

 

[soresu]

They made great sales with the old hybrid CPUs and now the same people that bought the old hybrids are going to buy the new ones.
They shot the consumers in the foot not themselves.

Great sales are usually dependent on the average dope that knows next to nothing about PC hardware and can easily be led around by the nose by sales staff in retail.

Said average consumer would probably not even notice that AVX512 was gone (if they even knew it was there in previous generations), but the more discerning enthusiasts would and hesitate to buy as a result.

Also I would argue that with the sheer effort over years they put into pushing AVX512 software development that they still definitely shot themselves in the foot - now when they introduce new instruction sets devs are going to be significantly more gunshy about implementing them without monetary compensation from Intel directly to that effect.

 

[A///]

it's almost poetic that the op's name is gideon and he chose to post this before anyone else.

 

[TheELF]

This line of thinking right here is the reason Intel is facing it's worst struggle in history.

Worst struggle in history=second highest amount of money they had in the last 12 years...(and highest total assets EVER)
Maybe you should explain what you consider struggle for a capitalistic company that is trying to make money.

Intel Cash on Hand 2010-2025 | INTC

Intel cash on hand from 2010 to 2025. Cash on hand can be defined as cash deposits at financial institutions that can immediately be withdrawn at any time, and investments maturing in one year or less that are highly liquid and therefore regarded as cash equivalents and reported with or near...

www.macrotrends.net

Intel Annual Cash on Hand (Millions of US $)
2022	$28,338
2021	$29,253
2020	$23,895
2019	$13,123
2018	$11,650
2017	$14,002
2016	$17,099
2015	$25,313
2014	$14,054
2013	$20,087
2012	$18,162
2011	$14,837
2010	$21,885

 

[TheELF]

but the more discerning enthusiasts would and hesitate to buy as a result.

A very small group of targets on the desktop, again not shooting themselves in the foot.
But now they aren't shooting all of the customers in the foot because as you said most of them don't even know, now it's only a very small group on the desktop that gets shot in the foot.

Also I would argue that with the sheer effort over years they put into pushing AVX512 software development that they still definitely shot themselves in the foot - now when they introduce new instruction sets devs are going to be significantly more gunshy about implementing them without monetary compensation from Intel directly to that effect.

Now when they introduce the new ISA all of that old software, and all the new software that is still using that old code will run faster and all the software houses that have this code will make ad campaigns stating x% faster on these new CPUs.
It's still just avx-512 or double 256 it doesn't require completely new code, unless I'm mistaken.

 

[soresu]

Now when they introduce the new ISA all of that old software, and all the new software that is still using that old code will run faster and all the software houses that have this code will make ad campaigns stating x% faster on these new CPUs.

when they introduce the new ISA is the salient point there.

For µArchs from ADL to the last one before AVX10.2 is implemented for consumer processors that is just wasted effort currently unless you are using a Skylake or earlier CPU.

Hence my point about Intel's actions causing developers to potentially become gunshy about implementing new instructions without monetary compensation from Intel directly.

Not that Intel are averse to such investments of course - they will doubtless blaze a trail to devs with $millions of greenbacks long before the new µArch is released for this and APX.

 

[soresu]

A very small group of targets on the desktop, again not shooting themselves in the foot.
But now they aren't shooting all of the customers in the foot because as you said most of them don't even know, now it's only a very small group on the desktop that gets shot in the foot.

I think it's not quite so cut and dry as that, certainly these days.

Yes you have the ingorant flat foots picking up a laptop from Target/Wallmart/PC World with nary a thought towards the action beyond the bite into their wallet, and you have the enthusiasts who ponder the pros and cons long before the HW is even released.

But with todays social media reach I would not be surprised to find that enthusiasts like Linus Tech Tips on Youtube and other such individuals/channels reviewing hardware on social media make a significant impact on a separate, more discerning market to the average consumer.

Not quite enough interest to be enthusiast, but enough interest in value for money to not blindly take whatever random salesperson A, B or C offer to you based on the stock that they are currently trying to get rid of ASAP.

 

[soresu]

it's almost poetic that the op's name is gideon and he chose to post this before anyone else.

I'm assuming that this is a literary reference that went over my head?

 

[Markfw]

Worst struggle in history=second highest amount of money they had in the last 12 years...(and highest total assets EVER)
Maybe you should explain what you consider struggle for a capitalistic company that is trying to make money.

Intel Cash on Hand 2010-2025 | INTC

Intel cash on hand from 2010 to 2025. Cash on hand can be defined as cash deposits at financial institutions that can immediately be withdrawn at any time, and investments maturing in one year or less that are highly liquid and therefore regarded as cash equivalents and reported with or near...

www.macrotrends.net

I don't know what he was thinking, but I think they are struggling since they have lost more marketshare, especially in servers than ever. And the layoffs. If you adjust those numbers for inflation, I am sure it will also change the picture. But marketshare affects future income.

 

[Tuna-Fish]

AVX10 sounds a bit like ARM's ARGON/SVE instruction set.

It's not like that at all. SVE's point is that it is designed in such a way that you can run the exact same codepath on CPUs with wildly different vector lengths, and other than running a different amount of iterations, get the same result.

AVX10 256/512 are not like that at all, the only convenience is that you can easily query for vector length, everything else is the job of the developer (or, more likely, the compiler). They are deranged if they think most devs are going to emit code that does anything other than supports some minimal common subset.

This is effectively giving up on the 64-byte vector length for client CPUs, while retaining the predication and other useful features of AVX-512. I am mildly disappointed, but really, the wide vectors were the least interesting and important part of AVX-512 anyway. A world with AVX10.2 256-bit is still much, much better than AVX2, and if they now start supporting it across the product line and do so consistently, then after about a decade, consumer stuff can finally start targeting it.

Worst struggle in history=second highest amount of money they had in the last 12 years...(and highest total assets EVER)
Maybe you should explain what you consider struggle for a capitalistic company that is trying to make money.

Intel Cash on Hand 2010-2025 | INTC

Intel cash on hand from 2010 to 2025. Cash on hand can be defined as cash deposits at financial institutions that can immediately be withdrawn at any time, and investments maturing in one year or less that are highly liquid and therefore regarded as cash equivalents and reported with or near...

www.macrotrends.net

Also look at the liabilities column. They have the most cash on hand and highest assets ever, because they took $11B of long-term debt last quarter, and are sitting on most of the cash. (This is not a criticism of this action, it was actually quite shrewd of them, as their ability to loan money at decent terms might be worse in the future, so might as well take out all the debt now and park it in treasuries until it's needed.)

Also total assets is not a good measure of a healthy company, because a lot of assets are very illiquid and might not be worth nearly as much as their book value if they had to be sold, and in the meantime they are just burning capital through depreciation.

I'm not an Intel doomer. I think there are a lot of smart people there, including people I know personally, and many of them are working really hard to turn the ship around and fix their problems. But it's really deluded to look at Intel's current financials and think that they are a healthy company. They really, really aren't. They have tens of billions of dollars invested in old, depreciating assets, their current product line is nowhere near good enough to regain their old position, and their manufacturing, the old crown jewel of the company, is still either lagging or at least hasn't proven it has caught up to the competition.