Intel Skylake / Kaby Lake

[Zucker2k]

Again, It's like you are not reading what I'm writing.

Let's do a virtual experiment.
Let's say you're part of the team in Intel which tests CPU's for the binning process (There is a team like, pretty big actually, they write the software to automate the process).

Let's say you are working on a CPU manufactured by Intel in the xx Process (The name doesn't matter).

Now, you build histogram of the speed and power consumed by each CPU out of the Fab per each month.

You do it for 4 years.
What do you expect to see?

I will tell you what you will see.
Let's assume the distribution is approximately Gaussian.
Hence you define it by Variance and the Mean.

With time the Mean of the speed will rise, the mean of the power will go down (Per speed) and the variance will get smaller.
Till now it happened (I can promise you that) on each and every process Intel used, Each of Them!
You saw that once with Haswell but in small marketing scale.

Till now, Intel has never used that as a "feature" since they had better things to show.
But now, when they have little to show (Process wise) they use it as a marketing feature.

That's what I'm saying, the improvement is there.
It has always been there in some ways.

When you play cards you can only play with the ones you have.
Intel, currently, doesn't have new process to show, so they market the regular over time improvements as a feature.

Funny thing is some users here sell it even better than Intel as this is the best thing ever.
The next step is, we never want to move to 10nm, we want 14+++ and then 14++++ .
This is just silly.
Intel markets what it can at this time.
It wished it could market better things like a real new process with much better performance.

Do you know the amount of work it takes to get a process to go from supporting 4 high performance cores to 6 high performance cores under the same relative tdp? Do you know the amount of resources Intel had to throw at this? This is going to be the biggest throughput performance jump from tock to tock since God knows when, and yet some people are still hanging onto nomenclature in order to bash Intel. I can only commend Intel's engineers for finding ways to squeeze out so much performance from the already great process 14nm+ process has proven to be. Looking at the problems Intel is having with the 10nm process, it'll be dodging a bullet with this release - at least for a while.

 

[Arachnotronic]

Again, It's like you are not reading what I'm writing.

Let's do a virtual experiment.
Let's say you're part of the team in Intel which tests CPU's for the binning process (There is a team like, pretty big actually, they write the software to automate the process).

Let's say you are working on a CPU manufactured by Intel in the xx Process (The name doesn't matter).

Now, you build histogram of the speed and power consumed by each CPU out of the Fab per each month.

You do it for 4 years.
What do you expect to see?

I will tell you what you will see.
Let's assume the distribution is approximately Gaussian.
Hence you define it by Variance and the Mean.

With time the Mean of the speed will rise, the mean of the power will go down (Per speed) and the variance will get smaller.
Till now it happened (I can promise you that) on each and every process Intel used, Each of Them!
You saw that once with Haswell but in small marketing scale.

Till now, Intel has never used that as a "feature" since they had better things to show.
But now, when they have little to show (Process wise) they use it as a marketing feature.

That's what I'm saying, the improvement is there.
It has always been there in some ways.

When you play cards you can only play with the ones you have.
Intel, currently, doesn't have new process to show, so they market the regular over time improvements as a feature.

Funny thing is some users here sell it even better than Intel as this is the best thing ever.
The next step is, we never want to move to 10nm, we want 14+++ and then 14++++ .
This is just silly.
Intel markets what it can at this time.
It wished it could market better things like a real new process with much better performance.

Your argument falls apart because it's fundamentally wrong. Again, with 14nm+ it wasn't just a question of the process maturing; there were changes to the process that you simply can't make and expect to keep manufacturing the same chips -- such as the fin height.

As far as your claim that "we want 14nm+++ and then 14++++," there is actually some truth to that. If all you care about is raw transistor performance/frequency, then you actually want to avoid shrinking because while you gain some performance with next generation transistors, you have to fight the increased parasitic capacitance that comes from pushing everything closer together.

By adding more "+" signs, Intel is improving transistor performance and not having to deal with the challenges that come from making things smaller. You also see this with other foundries, like Samsung and TSMC, who keep improving their older, more cost-effective processes.

The reason that companies want to shrink is purely a question of economics. For most products these days, you want to stuff more things in like bigger graphics, more cores, etc. so you want to shrink so you can keep throwing all of that stuff in without the size/cost becoming prohibitive.

Enthusiasts would probably love it if Intel did a 14nm+++ or a 14nm++++ and kept pushing frequencies up and maybe introducing new CPU architecture features, too. But that would be bad for mobile and mainstream desktop, since you want to keep adding features, which would not be feasible without a shrink after some point.

 

[psolord]

http://www.guru3d.com/news-story/european-core-i7-8700k-coffee-lake-prices-spotted-in-germany.html?

The Core i7 8700K with six-cores and one thread will cost €389,-

Wow, this must be a really strong thread! xD

 

[mikk]

https://browser.geekbench.com/v4/cpu/3928583

Another Geekbench 4 entry from i7-8700k.

 

[Shivansps]

Does anyone knows if CFL supports DDR3? im thinking they may have used DDR3 pins to provide power to support 2 more cores, that may be the reason of the incompatibility with 200 and 100.

I think Broadwell had a similar issue with 80 series chipsets, they used unused pins to provide power to the igp and edram, thus the incompatibility.

 

[FIVR]

Again, It's like you are not reading what I'm writing.

Let's do a virtual experiment.
Let's say you're part of the team in Intel which tests CPU's for the binning process (There is a team like, pretty big actually, they write the software to automate the process).

Let's say you are working on a CPU manufactured by Intel in the xx Process (The name doesn't matter).

Now, you build histogram of the speed and power consumed by each CPU out of the Fab per each month.

You do it for 4 years.
What do you expect to see?

I will tell you what you will see.
Let's assume the distribution is approximately Gaussian.
Hence you define it by Variance and the Mean.

With time the Mean of the speed will rise, the mean of the power will go down (Per speed) and the variance will get smaller.
Till now it happened (I can promise you that) on each and every process Intel used, Each of Them!
You saw that once with Haswell but in small marketing scale.

Till now, Intel has never used that as a "feature" since they had better things to show.
But now, when they have little to show (Process wise) they use it as a marketing feature.

That's what I'm saying, the improvement is there.
It has always been there in some ways.

When you play cards you can only play with the ones you have.
Intel, currently, doesn't have new process to show, so they market the regular over time improvements as a feature.

Funny thing is some users here sell it even better than Intel as this is the best thing ever.
The next step is, we never want to move to 10nm, we want 14+++ and then 14++++ .
This is just silly.
Intel markets what it can at this time.
It wished it could market better things like a real new process with much better performance.

Excellent post. Pretty much points out how silly the whole "14nm++" silliness is.


It is obvious to anybody that has been watching (and isn't completely biased) that intel is struggling to improve its process, and has resorted to secrecy and snake oil marketing tactics with their CPUs.

 

[eddman]

Again, It's like you are not reading what I'm writing.

Late skylakes' OC clock ceiling is still below Kaby lake. If both of them are on the same 14 nm process, don't you think they should OC the same on average.

AFA it's known, 14 and 14+ are actually, physically different.

 

[FIVR]

redacted

 

[Shivansps]

About the Intel PCI-E talk... Intel needs to increase DMI link to 8x, thats all they need to do, i prefer that over the Ryzen solution of having extra 4x PCI-E for a M2... Ryzen solution is really good for 1 M2, but moving data from the M2 to the sata or a M2 raid means data has to go thought the chipset link, thats what has to be avoided. Thats why Ryzen also has CPU satas. So data from the CPU M2 and CPU satas does not have to go to the chipset.

If Intel has a DMI x8, and x24 PCI-E links from the chipset that connects all the storage thats perfect, thats means moving data from SATA to M2, or M2 Raid data never goes thought the DMI link. They just need higher bandwidth.

Its that or completely integrate the PCH intro the CPU. What is not really a good idea, ive seen too many dead AM1 cpus, i suspect of the CPU usb.

 

[FIVR]

You're quoting Geekbench 3 scores... I'm talking about Geekbench 4...

LOL indeed...

Hm.. I stand corrected. Should have checked. Embarrassing.

 

[mikk]

Does anyone knows if CFL supports DDR3? im thinking they may have used DDR3 pins to provide power to support 2 more cores, that may be the reason of the incompatibility with 200 and 100.

There is only DDR4 support if nothing did change in later stages.

 

[Shivansps]

There is only DDR4 support if nothing did change in later stages.

mmmm.... thats may be the reason then.

 

[tamz_msc]

Your argument falls apart because it's fundamentally wrong. Again, with 14nm+ it wasn't just a question of the process maturing; there were changes to the process that you simply can't make and expect to keep manufacturing the same chips -- such as the fin height.

As far as your claim that "we want 14nm+++ and then 14++++," there is actually some truth to that. If all you care about is raw transistor performance/frequency, then you actually want to avoid shrinking because while you gain some performance with next generation transistors, you have to fight the increased parasitic capacitance that comes from pushing everything closer together.

By adding more "+" signs, Intel is improving transistor performance and not having to deal with the challenges that come from making things smaller. You also see this with other foundries, like Samsung and TSMC, who keep improving their older, more cost-effective processes.

The reason that companies want to shrink is purely a question of economics. For most products these days, you want to stuff more things in like bigger graphics, more cores, etc. so you want to shrink so you can keep throwing all of that stuff in without the size/cost becoming prohibitive.

Enthusiasts would probably love it if Intel did a 14nm+++ or a 14nm++++ and kept pushing frequencies up and maybe introducing new CPU architecture features, too. But that would be bad for mobile and mainstream desktop, since you want to keep adding features, which would not be feasible without a shrink after some point.

GF has 14nm LPE/LPP/LPU/LPC, TSMC has 16nm FF/FF+ and now a customized 12nm FFN - basically they're doing the same thing that Intel is doing, tweaking the initial node over time to maximize performance. Yet these are but a footnote in discussions when it comes to these manufacturers, while with Intel +/++/+++ is the headlining feature of their presentation decks.

 

[VirtualLarry]

If Intel has a DMI x8, and x24 PCI-E links from the chipset that connects all the storage thats perfect, thats means moving data from SATA to M2, or M2 Raid data never goes thought the DMI link. They just need higher bandwidth.

Not true. There is no device-to-device transfer protocols (well, SCSI used to have multi-master support, but we don't use SCSI any more), all use the CPU's memory controller to access host memory for buffering. So there's no improvement in having all of your I/O devices hanging off of the chipset, they have to go through the DMI link to the CPU, to access the RAM that's hanging off of the CPU's memory-controller anyways.

AMD's solution of the separate PCI-E x4 for an M.2 slot, IS a superior solution to Intel.

 

[Arachnotronic]

GF has 14nm LPE/LPP/LPU/LPC, TSMC has 16nm FF/FF+ and now a customized 12nm FFN - basically they're doing the same thing that Intel is doing, tweaking the initial node over time to maximize performance. Yet these are but a footnote in discussions when it comes to these manufacturers, while with Intel +/++/+++ is the headlining feature of their presentation decks.

Not really, TSMC makes a big deal about these enhancements on their conference calls, and you should keep in mind that both TSMC and Samsung have been using their respective "+" and "LPE/LPP/etc." designations for longer than Intel has.

Try again.

 

[Arachnotronic]

Just to put some context for those numbers:
8700K 5773 ST 24260 MT
7700K 5482 ST 17782 MT
1800X 4289 ST 20385 MT

Source for the 7700K/1800X scores: https://www.digitaltrends.com/processor-reviews/amd-ryzen-7-1800x-review/#/1-2

The ST score is prob helped by additional frequency + bigger/faster L3 cache. Also, GB4 is pretty sensitive to memory/cache bandwidth.

 

[Shivansps]

Not true. There is no device-to-device transfer protocols (well, SCSI used to have multi-master support, but we don't use SCSI any more), all use the CPU's memory controller to access host memory for buffering. So there's no improvement in having all of your I/O devices hanging off of the chipset, they have to go through the DMI link to the CPU, to access the RAM that's hanging off of the CPU's memory-controller anyways.

AMD's solution of the separate PCI-E x4 for an M.2 slot, IS a superior solution to Intel.

PCI-E devices can send data to each other directly using peer-to-peer or RDMA. The device must support it and they need to be on the same PCI-E root.

As far as i know, NVMe devices support this. I may be wrong here, but this ist how NVMe raid work?

Hell, Nvidia uses RDMA to copy data directly to a GPU on another system by doing GPU->NIC->NIC->GPU.

 

[Excessi0n]

The ST score is prob helped by additional frequency + bigger/faster L3 cache. Also, GB4 is pretty sensitive to memory/cache bandwidth.

Judging by my 6700k, that score is almost exactly what you get out of a 4.8 GHz Skylake core with stock cache and 2133 MHz memory. 4.8 core sounds too high for the stock single-core turbo (isn't it supposed to be 4.7?), so it's definitely benefiting from the cache. But the score isn't as high as you'd get if you had a significant memory overclock, so I'd bet cash that that test was run with generic 2133 or maybe 2400 memory.

 

[mikk]

Judging by my 6700k, that score is almost exactly what you get out of a 4.8 GHz Skylake core with stock cache and 2133 MHz memory. 4.8 core sounds too high for the stock single-core turbo (isn't it supposed to be 4.7?), so it's definitely benefiting from the cache. But the score isn't as high as you'd get if you had a significant memory overclock, so I'd bet cash that that test was run with generic 2133 or maybe 2400 memory.

1C Turbo is 4.7 Ghz, from where did you get 4.8 Ghz? Yes it's a rather low memory performance there, DDR4-2400 CL14 is faster on my i7-7700k. So it was running with either DDR4-2400 and a worse latency or DDR4-2133.

DDR4-2666 CL14 https://browser.geekbench.com/v4/cpu/3953226
DDR4-2400 CL14 https://browser.geekbench.com/v4/cpu/3953287

100 points difference for ST and 500 points for MT between 2400 and 2666. Imho the overall scores are way too much affected by memory speeds. This is a Geekbench flaw.

 

[Excessi0n]

1C Turbo is 4.7 Ghz, from where did you get 4.8 Ghz?

4.8 is what it would take to get that score without changing cache or memory. That's too high, so it must be benefiting from cache and/or memory to reach that score at a lower core clock.

 

[tamz_msc]

Not really, TSMC makes a big deal about these enhancements on their conference calls, and you should keep in mind that both TSMC and Samsung have been using their respective "+" and "LPE/LPP/etc." designations for longer than Intel has.

Try again.

They are not talked about in the same vein as Intel when they announce their "updates" to existing processes. It is nothing extraordinary with FinFET when you make revisions because now you have another dimension to optimize compared to planar transistors. Intel learned during the low yields of early 14nm that it would make more economic sense to tweak the parameters of the existing node instead of shrinking to a new node, but these changes won't be reflected in the nomenclature unless they're designated differently. So they went with this +/++ thing because every foundry knows that they're going to go against the laws of physics before they go against themselves.

Viewed in this light, this is nothing extraordinary as you and a few others are making it out to be.

 

[tamz_msc]

Do you know the amount of work it takes to get a process to go from supporting 4 high performance cores to 6 high performance cores under the same relative tdp? Do you know the amount of resources Intel had to throw at this? This is going to be the biggest throughput performance jump from tock to tock since God knows when, and yet some people are still hanging onto nomenclature in order to bash Intel. I can only commend Intel's engineers for finding ways to squeeze out so much performance from the already great process 14nm+ process has proven to be. Looking at the problems Intel is having with the 10nm process, it'll be dodging a bullet with this release - at least for a while.

Is that plain old rhetoric extolling the virtues of Intel's engineers or genuine curiosity?

If it's the latter, then the underlying principle is very simple. To fit more cores in the same TDP the cores must operate at a lower voltage. However, too low a voltage and the transistors might not work at all. So the only way to make them work at a lower voltage is to change their geometry, which means changing the parameters of the process.

 

[Arachnotronic]

They are not talked about in the same vein as Intel when they announce their "updates" to existing processes. It is nothing extraordinary with FinFET when you make revisions because now you have another dimension to optimize compared to planar transistors. Intel learned during the low yields of early 14nm that it would make more economic sense to tweak the parameters of the existing node instead of shrinking to a new node, but these changes won't be reflected in the nomenclature unless they're designated differently. So they went with this +/++ thing because every foundry knows that they're going to go against the laws of physics before they go against themselves.

Viewed in this light, this is nothing extraordinary as you and a few others are making it out to be.

Oh really?

Samsung Electronics, the world leader in advanced semiconductor technology, today announced it has added 11-nanometer (nm) FinFET process technology (11LPP, Low Power Plus) to its advanced foundry process portfolio, offering customers with an even wider range of options for their next-generation products.



Through further scaling from the earlier 14LPP process, 11LPP delivers up to 15 percent higher performance and up to 10 percent chip area reduction with the same power consumption.

https://news.samsung.com/global/sam...-new-11nm-lpp-and-7nm-lpp-with-euv-technology

 

[coercitiv]

This is a Geekbench flaw.

This is why I don't even look at GB scores anymore, I find it almost useless when trying to evaluate unreleased hardware. It may be perfectly acceptable when doing apples to apples comparisons (especially for controlled testing) but everything else is downright unreliable in my view.

 

[tamz_msc]

Oh really?



https://news.samsung.com/global/sam...-new-11nm-lpp-and-7nm-lpp-with-euv-technology

A foundry announcing new options for customers in addition to what it offers currently is not surprising. A chip-maker which is failing to start off its own foundry business and desperately highlighting it's theoretical superiority in order to market itself better shouldn't also come as anything surprising.

Manufacturing requirements change, node parameters also change. Why make such a big deal out of it?