Intel Skylake / Kaby Lake

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moonbogg

moonbogg

Lifer
Jan 8, 2011
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Bouowmx said:
There isn't any confusion. 16 PCIE lanes from CPU. 24 from Z[23]70 chipset, or PCH. CPU-PCH is linked by DMI 3.0, equivalent to PCIE 3.0 x4. All the same as before.

I've said the following about sound card: You put the sound card in a slot that uses lanes from PCH. You want to gobble 8 lanes for a sound card that only needs a few MB/s?
Click to expand...

So you can have a sound card and an X16 GPU at the same time? I think 16 lanes is unforgivable and results in platform death. I won't buy it. What if someone wants something over the top, such as (gasp) a sound card AND an M.2 SSD?! Whoa, now what? Don't they load those boards with all kinds of M.2 slots and a ton of PCI-E slots? Why? You can't use them, lol. Not with 16 lanes. What a pile of suck.
 
crashtech

crashtech

Lifer
Jan 4, 2013
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I buy motherboards with highly rated sound on board; subjectively I can't tell the difference between the boards I have chosen and discrete DACs. This might be due to hearing loss, vast improvements made in onboard audio in recent years, or both, but really, vanishingly few users feel the need for a sound card if they've chosen their board well. My main system has one M.2 SSD, one SATA SSD, and one GPU. Coffee Lake will work fine for me.
 
B

Bouowmx

Golden Member
Nov 13, 2016
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Yes, you can have 16 lanes from CPU dedicated to GPU, and a M.2 PCIE SSD and sound card with lanes from PCH, all at the same time.

Now with multiple M.2 PCIE SSDs connected to PCH, if each are individually fast enough and all are simultaneously doing sequential read, DMI 3.0 can bottleneck them.

The more extravagant the expansions, the more you will have to look into which slots are switched. At this point, PEX switch may be needed, and one might ask, is the client platform appropriate for this user?
 
moonbogg

moonbogg

Lifer
Jan 8, 2011
10,731
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Bouowmx said:
Yes, you can have 16 lanes from CPU dedicated to GPU, and a M.2 PCIE SSD and sound card with lanes from PCH, all at the same time.

Now with multiple M.2 PCIE SSDs connected to PCH, if each are individually fast enough and all are simultaneously doing sequential read, DMI 3.0 can bottleneck them.

The more extravagant the expansions, the more you will have to look into which slots are switched. At this point, PEX switch may be needed, and one might ask, is the client platform appropriate for this user?
Click to expand...

Is that the case? I can see how neither a sound card or SSD would use a lot of bandwidth during gameplay, and if it doesn't reduce the GPU's lane availability down from 16, then that's cool I suppose. If that's the case then I guess I'm back to being excited and far less pissed off. THANKS MAN!
 
B

Bouowmx

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Nov 13, 2016
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2*(6 Gbit/s)/8 (2 SATA SSDs) + 2500 MB/s (PCIE SSD) + 72 MB/s (Blu-ray 16x) = 4072 MB/s

Now that is right at the limit of one direction of DMI 3.0, 4 GB/s, not including USB, Ethernet, and other devices. Do you simultaneously read from all devices often enough this bottleneck is an important issue?
 
coercitiv

coercitiv

Diamond Member
Jan 24, 2014
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AtenRa said:
ok thanks, any links for that ??
Click to expand...
Anandtech 8th gen coverage - mobile Kaby Lake Refresh is 14nm+, desktop Coffee Lake is 14nm++, mobile Cannon Lake is 10nm.
We expect that Intel’s 8th Generation will eventually contain three core designs of product on three different process design nodes: the launch today is Kaby Lake Refresh on 14+, and in the future we will see Coffee Lake on 14++ become part of the 8th Gen, as well as Cannon Lake on 10nm.
Click to expand...

EDIT: typo exactly where it hurt the most
 
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LTC8K6

LTC8K6

Lifer
Mar 10, 2004
28,520
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PeterScott

PeterScott

Platinum Member
Jul 7, 2017
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maddie said:
And here I was thinking that this was expected to last some here for years. Wonder the relative speeds of GPUs in say 5 yrs?
Click to expand...

You do know that you still have X16 available for one slot, for the GPU if it becomes an absolute benefit.

At some point you have to stop making mountains out of motes of dust (this isn't even a molehill size issue).
 
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D

Drazick

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May 27, 2009
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@Arachnotronic, You're again, handling Intel with credit while no other company will have the same credit from you.

14+ / 14++ are both marketing thing by definition as they describe point in time for a manufacturing process.

Any process in the past Intel used got better and better in time.
In the past since real features (CPU Features) cadence was high enough there was no need to define point in time for the process.

In our days there is nothing new to put on the table so Intel, doing right for marketing point of view as it works on you, just said let's market in time process by discrete points in time.

The real question here is has the improvements in the 14++ / 14+ are something beyond anything happened in previous processes?

I'd bet not.
But unless you have inside data (Not marketing data, as the logic of those is explained above) don't just throw Intel Marketing agenda as it was the truth, the whole truth and nothing bu the truth.
 
A

Ajay

Lifer
Jan 8, 2001
16,094
8,112
136
Drazick said:
@Arachnotronic, You're again, handling Intel with credit while no other company will have the same credit from you.

14+ / 14++ are both marketing thing by definition as they describe point in time for a manufacturing process.

Any process in the past Intel used got better and better in time.
In the past since real features (CPU Features) cadence was high enough there was no need to define point in time for the process.

In our days there is nothing new to put on the table so Intel, doing right for marketing point of view as it works on you, just said let's market in time process by discrete points in time.

The real question here is has the improvements in the 14++ / 14+ are something beyond anything happened in previous processes?

I'd bet not.
But unless you have inside data (Not marketing data, as the logic of those is explained above) don't just throw Intel Marketing agenda as it was the truth, the whole truth and nothing bu the truth.
Click to expand...

Oh man, just stop already - K?
Bunch of b*itchy little children :angry:
 
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LTC8K6

LTC8K6

Lifer
Mar 10, 2004
28,520
1,575
126
Drazick said:
@Arachnotronic, You're again, handling Intel with credit while no other company will have the same credit from you.

14+ / 14++ are both marketing thing by definition as they describe point in time for a manufacturing process.

Any process in the past Intel used got better and better in time.
In the past since real features (CPU Features) cadence was high enough there was no need to define point in time for the process.

In our days there is nothing new to put on the table so Intel, doing right for marketing point of view as it works on you, just said let's market in time process by discrete points in time.

The real question here is has the improvements in the 14++ / 14+ are something beyond anything happened in previous processes?

I'd bet not.
But unless you have inside data (Not marketing data, as the logic of those is explained above) don't just throw Intel Marketing agenda as it was the truth, the whole truth and nothing bu the truth.
Click to expand...
Yes, we have seen the mobile chips' ability to boost higher, and for longer periods, within the same TDP envelope for 14+ over 14. This was a real-world indication that 14+ was better than 14 as far as overall efficiency. We have also seen the 14+ KL desktop chips have similar efficiency gains over the 14 SL chips. All of this is well known, so I am not sure why it keeps coming up. It was well reported at the time the 14+ mobile chips were released, and at the time the 14+ desktop chips were released.

There's no reason to think that 14++ is not more efficient again than 14+, regardless of marketing talk or fanboy talk.
 
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Jan Olšan

Jan Olšan

Senior member
Jan 12, 2017
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Arachnotronic said:
Yep, relaxing the gate pitch from 70nm to 84nm, which will lead to some die size increase.
Click to expand...

Are we sure this is actually global rule of the process used? I'd say this (and the 14+/14++ designations too) might actually be a thing that is coupled with the design of the individual chip. The choice to use bigger transistors is always there when designing - not all transistors on chip are the same, to the contrary - you use bigger or smaller ones based on your needs - for example if you want to drive the whole at higher clocks. And from the look of it, the density loss is not global, so they probably did maintain size of non-critical transistors and only enlarged the ones needed for the desired clock boost.

https://ask.fm/tom_forsyth/answers/141115563411

Also note that there's no thing thing as "a transistor". They're all different sizes. If they need to switch fast, or drive a long wire, or drive twenty other transistors, they usually need to be bigger. If they just need to talk to one transistor right beside them, then they can be smaller. Because of this, the "transistor count" metrics are usually just made up - they take the area of the chip, divide by the smallest transistor they can make, and there's you go - an impressively big number for marketing to use.
Click to expand...

Anyway, I don't think calling these intra-node improvements 14+ is something to be ashamed of. They could go and call it 12nm (not sure TSMC and/or Samsung is the same situation, but they seem to have a suspiciously high number of nodes lately, like 8,7,6,5,4nm...)
 
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frozentundra123456

frozentundra123456

Lifer
Aug 11, 2008
10,451
642
126
LTC8K6 said:
Yes, we have seen the mobile chips' ability to boost higher, and for longer periods, within the same TDP envelope for 14+ over 14. This was a real-world indication that 14+ was better than 14 as far as overall efficiency. We have also seen the 14+ KL desktop chips have similar efficiency gains over the 14 SL chips. All of this is well known, so I am not sure why it keeps coming up. It was well reported at the time the 14+ mobile chips were released, and at the time the 14+ desktop chips were released.

There's no reason to think that 14++ is not more efficient again than 14+, regardless of marketing talk or fanboy talk.
Click to expand...
Well in all the arguing, there is a third possibility-- Probably is some of both. 14nm+ brought gains in mobile brought performance gains similar to some die shrinks. Who knows how much 14nm++ will bring? Obviously, it is a "marketing" point as well, just like every company tries to make its products sound new. That does not mean any gains we see are any less real.
 
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LTC8K6

LTC8K6

Lifer
Mar 10, 2004
28,520
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The 6700 was limited to 3.7ghz for 4 cores for a 65W TDP.

The 7700 could run 4 cores at 4ghz for a 65W TDP.

The 8700 should be a 6 core 65W TDP chip that can run all six cores at 4.2 or 4.3 ghz.
 
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