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Intel Skylake / Kaby Lake

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hnizdo

Member
Aug 11, 2017
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Ryzen/Threadriper/Epyc SoC design is "very smart and innovative".
Its cost effective. Definitelly not innovative. Multi chip design was abandoned long ago for the reason, repeatedly proven by Ryzen's multi-CCX heavy performance hit in some applications. Thats why Intel is working with monolithic designs as far as possible.
 
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Zucker2k

Golden Member
Feb 15, 2006
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What,:D here we go again or "Speed Comedy Club for beginers=you failed absurdly".

How do you even compare, just one example i5 7600/4/4 220$ CPU vs R5 1600/6/12 CPU 215$?

https://www.newegg.com/Product/Product.aspx?Item=N82E16819113435

https://www.newegg.com/Product/Product.aspx?Item=N82E16819117729

Ryzen/Threadriper/Epyc SoC design is "very smart and innovative". But that is classic AMD, when they have smart leadership+Jim Keller, well the results are very obvious.:cool:

http://www.tomshardware.com/news/amd-threadripper-epyc-mcm-cost,35306.html


Here we go again.
 
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coercitiv

Diamond Member
Jan 24, 2014
4,363
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I don't think there will be any reviews. Just read any review of the 7900X and add 10% or so.
Isn't the 7920X based on a different die? I'd rather see it taken through the usual paces, would be a nice opportunity to check the current state of the platform together with performance and thermals for the new chip.
 

Asterox

Senior member
May 15, 2012
531
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Its cost effective. Definitelly not innovative. Multi chip design was abandoned long ago for the reason, repeatedly proven by Ryzen's multi-CCX heavy performance hit in some applications. Thats why Intel is working with monolithic designs as far as possible.
Multi Chip was never abandoned, just only delayed for the future, or when you have much superior manufacturing proces. In the future Intel is heading/is forced in that direction, or "glued CPU desing".

AMD was first with "superglue", and "very expensive R5 1600" is just one example of that failed glued non-inovative CPU design.:cool:

http://www.pcworld.com/article/3185875/hardware/future-intel-cpus-could-be-cobbled-together-using-different-parts.html
 

hnizdo

Member
Aug 11, 2017
33
16
41
Multi Chip was never abandoned, just only delayed for the future
Yes, it was "delayed" (it wasnt really, its in use) until there was no other option (like smaller process), despite its cheaper solution :) It has performance impact because of interconnect necessity and slow cache sharing.

BTW Ryzen is not multichip. Its single chip with module design. This wasnt invented by AMD either.
You were referring Threadripper and Epic. Both are multi chip. It was first used by IBM at 1970. In x86 world by Intel at 1995 (PentiumPro).
Multi chip desing price saving not affecting Ryzen.

Actually I think you are just trolling.
 
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eddman

Senior member
Dec 28, 2010
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Multi Chip was never abandoned, just only delayed for the future, or when you have much superior manufacturing proces. In the future Intel is heading/is forced in that direction, or "glued CPU desing".

AMD was first with "superglue", and "very expensive R5 1600" is just one example of that failed glued non-inovative CPU design.:cool:

http://www.pcworld.com/article/3185875/hardware/future-intel-cpus-could-be-cobbled-together-using-different-parts.html
That's not MCM. It's EMIB. Also, (someone else could correct me if I'm wrong) it seems that intel will still put the cores/processor block still on a single, monolithic die. Only the non-processor blocks will be on separate dies.

Copying between storage devices still takes buffers for the data payload located in system memory, i.e. in RAM behind the CPU's memory controller. This is true for NVMe, AHCI, UASP, classic USB storage, and other storage interfaces.
Do you mean that between-storage transfers are always buffered or just in some cases? If I, for example, copy a 10 GB file from storage A to B, would the entire file go through the DMI and RAM? That would be extremely inefficient.
 

StefanR5R

Elite Member
Dec 10, 2016
4,077
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Re DMI as a potential bottleneck,
Copying between storage devices still takes buffers for the data payload located in system memory, i.e. in RAM behind the CPU's memory controller. This is true for NVMe, AHCI, UASP, classic USB storage, and other storage interfaces.
Do you mean that between-storage transfers are always buffered or just in some cases?
Always.

Data transfers from/to a mass storage device (in particular, block oriented storage device with DMA capability) mean the device writes to/ reads from system memory regions which the operating system allocated for this purpose, layed them out suitably, and communicated their locations to the (DMA capable) device according to the interface model. The device communicates back to the system when done with writing or reading a buffer. (The precise way differs again between interface models, i.e. NVMe, AHCI, etc..)

In order to transfer between two devices without involving system memory, the devices would have to have suitably large onboard buffers and would have to follow a common protocol for buffer management.
If I, for example, copy a 10 GB file from storage A to B, would the entire file go through the DMI and RAM? That would be extremely inefficient.
In order to implement it as direct device-to-device copy, and get such a direct communication to perform at least as well as the present copying with system RAM in between, would probably turn out rather costly and wasteful. Performance metrics include throughput, latency, error handling...
 
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coffeeblues

Member
Jun 23, 2017
49
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Intel Xeon W, in similar vein to the former E5-1600 series: http://www.anandtech.com/show/11775/intel-launches-xeon-w-cpus-for-workstations

Depending on how you look at it, Xeon W is Skylake-SP to socket R, or Skylake-X with ECC and other professional features.

48 PCIe lanes supported, up from 44.

New chipset required: C422, which may be cross-compatible with X299.
Looks like Intel is going to continue hard locked ecc/non ecc split that started with skylake desktop platform,
C422 board - http://b2b.gigabyte.com/Server-Motherboard/MW51-HP0-rev-10#ov .
 

MarkPost

Member
Mar 1, 2017
160
75
101
Intel BX80684I58600K Core i5-8600K 3.7GHz 6-Core

65W TDP, Turbo 4.2GHz, 9MB L3 Cache, GT2 Graphics, Socket-1151-V2
$314.00

Intel BX80684I78700 Core i7-8700 3.7GHz 6-Core

65W TDP, Turbo 4.2GHz, 12MB L3 Cache, GT2 Graphics, Socket-1151-V2
$368.00

Intel BX80684I78700K Core i7-8700K 3.8GHz 6-Core

95W TDP, Turbo 4.3GHz, 12MB L3 Cache, GT2 Graphics, Socket-1151-V2
$428.00

source -> http://gamepc.com/shop/productscategory?list=CPU
so its the same 1-core turbo than 7700k, isn it?
 

MarkPost

Member
Mar 1, 2017
160
75
101
1. These prices, Canadian, have already been posted many pages back;
2. No 4.3 is the all-core turbo...this is not news...this has been known for a while.
I know 4.3 is all core turbo. But it states 1-core turbo = 4.5. Thats what I'm asking for

EDIT: as far as I know GamePC is an US comp
 

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