Intel Skylake / Kaby Lake

[Phynaz]

And also: why doesn't CFL have Gen10?

I don't think Intel has ever said anything about Gen 10. As far as I'm aware anything about Gen 10 has been just a rumor, such as my favorite site (WCCF) stating a year and half ago that KBL would have Gen 10 graphics.
(Because you know, Pakistan is the new Silicon Valley - Pakistani web sites I'm sure have unprecedented access to Intel specifications )

 

[RichUK]

Does anyone expect kaby Lake to run cooler?

 

[Sweepr]

Core i7-7700 & i7-7700K on sale in China

https://world.taobao.com/item/541397623741.htm?fromSite=main
https://world.taobao.com/item/542171377422.htm?fromSite=main

Another curiosity: the EDA for the Kaby Lake-S chips listed (and later removed) by ShopBLT a few weeks ago was November 22th. I think (some) stores already have the chips, just waiting for the green light from Intel to start selling them.

 

[VirtualLarry]

When is Intel going to phase out production of SKL CPUs... or do you think that they have done so already?

 

[Arachnotronic]

When is Intel going to phase out production of SKL CPUs... or do you think that they have done so already?

They will keep them in production for a while, though expect quantities to be limited. 4790K is still in production, for example -- it hasn't been moved to EOL yet. Though if you for some reason want a 4790K (don't know why anybody would buy one now), they'll probably be gone soon.

http://ark.intel.com/products/80807/Intel-Core-i7-4790K-Processor-8M-Cache-up-to-4_40-GHz

Last order date for 3770K Ivy Bridge was in late 2014, nearly three years after launch.

Last order date is December 26, 2014
Last shipment date is June 5, 2015

http://www.cpu-world.com/CPUs/Core_i7/Intel-Core i7-3770K.html

 

[Nothingness]

AVX is not much use, HT is much better. There is a 20-25% boost for many applications, it helps dualcore CPUs more than Quadcore CPUs. Basically in all games nowadays. AVX use cases are very limited for consumer. X264 and even more x265 benefits from it but not with 20-25%.

Segmentation based on instructions is simply stupid. It creates fragmentation and by not making all instructions available on all CPU you just make sure that many developers will never use them because they don't have time and resources to develop multiple code paths. Chicken and egg problem.

But I agree with you that HT is likely more useful for dual cores, my previous post was more about self-derision. I want my AVX-512

 

[Arachnotronic]

Segmentation based on instructions is simply stupid. It creates fragmentation and by not making all instructions available on all CPU you just make sure that many developers will never use them because they don't have time and resources to develop multiple code paths. Chicken and egg problem.

But I agree with you that HT is likely more useful for dual cores, my previous post was more about self-derision. I want my AVX-512

AVX-512 won't find its way onto mainstream desktop CPUs for a long time, IMO. Certainly not at least until Icelake, but I would wager that even then AVX-512 will be kept off the client stuff.

 

[lolfail9001]

AVX-512 won't find its way onto mainstream desktop CPUs for a long time, IMO. Certainly not at least until Icelake, but I would wager that even then AVX-512 will be kept off the client stuff.

Fairly positive AVX-512 is confirmed for Cannonlake via compiler patches.

Segmentation based on instructions is simply stupid. It creates fragmentation and by not making all instructions available on all CPU you just make sure that many developers will never use them because they don't have time and resources to develop multiple code paths. Chicken and egg problem.

But I agree with you that HT is likely more useful for dual cores, my previous post was more about self-derision. I want my AVX-512

Devs that want AVX-256 could not care less what people buying under $100 CPUs have.

 

[Arachnotronic]

Fairly positive AVX-512 is confirmed for Cannonlake via compiler patches.

High performance laptops as well as desktops will not get Cannon Lake it seems, they will get Coffee Lake which is Kaby Lake which is Skylake. And even if CNL 2+2 has AVX-512 on the die, no way it's going to be enabled for 2-in-1 convertibles and thin laptops.

 

[Nothingness]

Devs that want AVX-256 could not care less what people buying under $100 CPUs have.

Yeah, they want to be sure their software will never run on a significant part of the market

 

[Arachnotronic]

Yeah, they want to be sure their software will never run on a significant part of the market

I don't think the kinds of people who buy Celeron/Pentium chips are going to be the kinds of folks who run software that could take advantage of AVX2.

Really, these advanced SIMD features are put in there primarily for workstation/HPC/datacenter customers, and they are not buying any CPUs without AVX2 these days. Soon, they won't be buying anything without AVX-512

 

[Maxima1]

High performance laptops as well as desktops will not get Cannon Lake it seems, they will get Coffee Lake which is Kaby Lake which is Skylake. And even if CNL 2+2 has AVX-512 on the die, no way it's going to be enabled for 2-in-1 convertibles and thin laptops.

So CFL isn't based on CNL (e.g. no FIVR)? I haven't been paying attention recently.

 

[jpiniero]

So CFL isn't based on CNL (e.g. no FIVR)? I haven't been paying attention recently.

At this point it's unknown.

 

[Nothingness]

I don't think the kinds of people who buy Celeron/Pentium chips are going to be the kinds of folks who run software that could take advantage of AVX2.

Really, these advanced SIMD features are put in there primarily for workstation/HPC/datacenter customers, and they are not buying any CPUs without AVX2 these days. Soon, they won't be buying anything without AVX-512

AVX 2 has interesting uses many people are not aware of. Most think it's only about transcoding (which is a valid use even on Celeron and Pentium). But it's useful in 3d drivers, software rendering (think of small bunch of data not worth transfering to GPU, or accurate emulators), string operations (which are used everywhere).

This reminds me of when NVIDIA stupidly decided ARM NEON (aka AdvSIMD) was not needed in Tegra. This resulted in Android assuming NEON isn't available even on ARMv7-A CPU.

Anyway enough off-topic

 

[mikk]

There is only 1 thing that does not work out: there is still no evidence to it being a 32 core part from what i see.

There is also no evidence that it's a 28C part.

Plus, there is something inherently wrong with jumping 8 cores up in a single gen, if you ask me.

18 -->24 = +33%
24 -->32= +33%


Same increase.

 

[lolfail9001]

There is also no evidence that it's a 28C part.

There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.

Same increase.

HSW-EP to BDW-EP was a node shrink, however. These generally land a large improvement (compare Westmere-EX to IVB-EX).

On same node we only had a 15C->18C jump (IVB HCC to HSW HCC). Not to mention, 2 more memory channels and few more PCI-E lanes.

 

[Arachnotronic]

There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.

HSW-EP to BDW-EP was a node shrink, however. These generally land a large improvement (compare Westmere-EX to IVB-EX).

On same node we only had a 15C->18C jump (IVB HCC to HSW HCC). Not to mention, 2 more memory channels and few more PCI-E lanes.

It's important to look at the end of one node to the end of another.

End of 32nm -> 8 core SNB-EP
End of 22nm -> 18 core HSW-EP
End of 14nm -> 32 core (?) SKL-EP.

This would mean that despite the better-than-average scaling that Intel saw in going from 22nm -> 14nm, it's getting a smaller increase in cores than it did with 22nm relative to 32nm.

I think 32 cores is perfectly plausible.

 

[lolfail9001]

End of 32nm -> 8 core SNB-EP

10 core Westmere-EX did exist on 32nm, so if 32 cores are real, it is same scaling as Westmere-EX to HSW-EX

I think 32 cores is perfectly plausible.

Of course it is, but the only evidence we have of it are Chinese bootleggers claiming it does.

 

[Arachnotronic]

10 core Westmere-EX did exist on 32nm, so if 32 cores are real, it is same scaling as Westmere-EX to HSW-EX

Of course it is, but the only evidence we have of it are Chinese bootleggers claiming it does.

Oh good call I forgot about WSM-EX.

 

[mikk]

There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.

Makes no sense. Do you have evidence that Xeon E5-2699 V5 is a 28 core SKU? I bet you don't, means your evidence is meaningless. It is a native 32 core Die according to Computerbase, based on informations they received from events like IDF or Hotchips, they are saying that a bigger SKU than 28C was no surprise behind closed doors. Now think twice.

 

[Sweepr]

Iris Pro lives through Xeon. Too bad it's BGA, a LGA version of this SKU could have replaced Broadwell-C for desktops.

Xeon E3-1585 v5 (65W TDP) with Iris Pro P580

www.ark-pc.co.jp/i/12102517

Already at the events in the summer like IDF 2016 and Hot Chips ComputerBase had repeatedly received the information that the Skylake server has not only 28 but 32 cores. What is now reported as direct "AMD Zen counter" by Intel

www.computerbase.de/2016-11/skylake-ep-ex-32-kerne-cpu-xeon

 

[jpiniero]

Iris Pro lives through Xeon. Too bad it's BGA, a LGA version of this SKU could have replaced Broadwell-C for desktops.

Xeon E3-1585 v5 (65W TDP) with Iris Pro P580

www.ark-pc.co.jp/i/12102517

That model was released in Q2.

 

[Sweepr]

But this is one of the first 'design wins' I could find.

 

[IntelUser2000]

There is, however, evidence of 28C samples being shipped around. No evidence of 32c one.

HSW-EP to BDW-EP was a node shrink, however. These generally land a large improvement (compare Westmere-EX to IVB-EX).

On same node we only had a 15C->18C jump (IVB HCC to HSW HCC). Not to mention, 2 more memory channels and few more PCI-E lanes.

The core count increase at the same process is significant too. They increase it to the limits of traditional big die size. I don't think engineers look at the amount of cores and think "oh an increase of 8 is too much", or "we must get xx% increase in cores" but rather they take their design within the limitations of process/die size/power use/clock frequency, and it comes out to be what it is.

You don't see "Tick" chips with 6xxmm2 die size. It's always for the "Tock" chips. In that sense, 14nm has quite a bit of room to go considering Broadwell EP is 456mm2. Haswell EP was 660mm2. In contrast, Ivy Bridge was rather large at 541mm2. The growth on 14nm comes with Skylake. 6xxmm2 sizes were traditionally reserved for Itanium and Xeon Phi chips, but they weren't on a bleeding edge process either.

 

[lolfail9001]

Makes no sense. Do you have evidence that Xeon E5-2699 V5 is a 28 core SKU? I bet you don't, means your evidence is meaningless. It is a native 32 core Die according to Computerbase, based on informations they received from events like IDF or Hotchips, they are saying that a bigger SKU than 28C was no surprise behind closed doors. Now think twice.

Nope, but 28C is the largest core count on samples shipped earlier. Now, if it is indeed 32C, great. But so far the only evidence i see is hearsay and Chinese folks claiming that.

You don't see "Tick" chips with 6xxmm2 die size. It's always for the "Tock" chips. In that sense, 14nm has quite a bit of room to go considering Broadwell EP is 456mm2. Haswell EP was 660mm2. In contrast, Ivy Bridge was rather large at 541mm2. The growth on 14nm comes with Skylake. 6xxmm2 sizes were traditionally reserved for Itanium and Xeon Phi chips, but they weren't on a bleeding edge process either.

Considering that Skylake XCC has more PCI-E lanes, another interconnect, 2 more memory channels, having 8 more cores on top of that would presumably increase the die size way beyond land of reason. I mean, replacing a DDR3 controller with DDR4 one and adding 3 more cores added a whole 120mm^2 of die size. I would imagine adding 8 more cores would add similar amount of die size. And then we have MOAR uncore to work with.

On the other hand, presumably L3 Cache in Skylake XCC is also much smaller, so maybe that does make it reasonable.