Discussion Intel Nova Lake in H2-2026: Discussion Threads

[igor_kavinski]

who even buys strix point???

Yeah, I have to agree that AMD dropped the ball on this one. The only great thing I read about it is that the Beelink Strix Point mini PC does not throttle and keeps going at full speed during all core workloads. Previous gens would throttle.

Personally I would choose a Strix Halo mini PC over a Strix Point one.

 

[LightningZ71]

AMD hobbled Strix Point by converting the MALL cache into a die waste unit. With 16MB of MALL cache, the 8WU iGPU would be in the RX 6400/6500 performance range easily.

 

[fastandfurious6]

even with that... not a good option

why get only 4 full + 8 dense cores when you can get 16 full cores + 40 whole CUs with halo even in handhelds....

 

[LightningZ71]

Because the vast majority of games are performance restricted on the CPU side by 4 or less threads, Most by two or less. See the performance of the singular Lunar Lake handheld out there? It only has 4 performance cores and can hang with or best all the rest with the updated firmware.

 

[511]

https://videocardz.com/newz/intel-nova-lake-s-cpu-with-28-cores-listed-in-shipping-manifest

 

[coercitiv]

https://videocardz.com/newz/intel-nova-lake-s-cpu-with-28-cores-listed-in-shipping-manifest

That article is the embodiment of "modern leak culture": he haven't seen leaks about this SKU before, therefore it must be the refresh of the the chips they will launch after they're done refreshing their current lineup.

PS: I see they updated the article from it's original form this morning, they no longer speak of a Nova Lake Refresh.

 

[511]

That article is the embodiment of "modern leak culture":

Modern Media is cooked next time I should post the Shipping Manifest this means NVL Has already Taped out.

 

[Tigerick]

Intel Accepts That Arrow Lake CPUs Weren't A Good Desktop Offering, Says Nova Lake Will Address The High-End Desktop Market Better Next Year

Intel has highlighted that Nova Lake will address the high-end desktop CPU market better than its Arrow Lake CPUs in 2026.

wccftech.com

Interesting and honest comments from Intel's CFO:

As you know, we kind of fumbled the football on the desktop side, particularly high performance desktop side. So we’re as you kind of look at share on a dollar basis versus a unit basis, we don’t perform as well and it’s mostly because of this high end desktop business that we didn’t have a good offering this year. But Nova Lake, which is the next product, is a more complete set of SKUs.

At least he admitted ARL is bad and we all know that. Let's see how N2-based 8+16 (16+32) compute dies perform...

Doesn’t get us quite there [Diamond Rapids]. I mean, does in certain cases, the performance is actually better. But in other cases, it’s not. And so we’ve got more work to do to finally get to a place and it’s really not I think Lip Bu actually named the product in some forum, but Coral Rapids is the next product. And that’s our real opportunity, I think, to begin to take a really good step forward.

I would say as Lip Bu has come in, he has really rolled up his sleeves and torn apart that strategy and looked at the roadmap and there were pockets there were gaps quite honestly in that roadmap that we were allowing that Lip Bu is not going to allow and so particularly around multi threading. And so we will be adjusting the roadmap to make sure that we are listening to customers and delivering products that customers want and need.

"In other cases, it's not." He most likely refers to MT performance due to lack of HT.

Coral Rapids is the official codename for next-gen Xeon P-core CPU which comes with HT.

Have you wonder why PTL, CWF and DMR (NVL also) all come without HT under leadership of Pat? Everyone knows HT is improving MT performance by increasing 5% of die area only and yet. Hoho, the same for ditching AVX-512 and then bring it back...

 

[Geddagod]

Intel Accepts That Arrow Lake CPUs Weren't A Good Desktop Offering, Says Nova Lake Will Address The High-End Desktop Market Better Next Year

Intel has highlighted that Nova Lake will address the high-end desktop CPU market better than its Arrow Lake CPUs in 2026.

wccftech.com

Interesting and honest comments from Intel's CFO:

At least he admitted ARL is bad and we all know that. Let's see how N2-based 8+16 (16+32) compute dies perform...

"In other cases, it's not." He most likely refers to MT performance due to lack of HT.

Coral Rapids is the official codename for next-gen Xeon P-core CPU which comes with HT.

Have you wonder why PTL, CWF and DMR (NVL also) all come without HT under leadership of Pat? Everyone knows HT is improving MT performance by increasing 10-20% of die area only and yet. Hoho, the same for ditching AVX-512 and then bring it back...

Not even 10-20% of die area. AMD claims the area cost of their SMT implementation in Zen 5 is sub 5% IIRC. The area cost seems to be extremely minimal.

 

[Tigerick]

Not even 10-20% of die area. AMD claims the area cost of their SMT implementation in Zen 5 is sub 5% IIRC. The area cost seems to be extremely minimal.

Tks, I have changed the percentage. My question remains: why does Pat ditch HT which will greatly improve performance of MT?

 

[511]

Tks, I have changed the percentage. My question remains: why does Pat ditch HT which will greatly improve performance of MT?

The P core team sold the idea they can make a better and denser core with killing HT and the development time would be faster without security issues.

 

[Thibsie]

The P core team sold the idea they can make a better and denser core with killing HT and the development time would be faster without security issues.

But P core teams being what they are, they probably were just trying to hide their own shortcomings.

 

[511]

But P core teams being what they are, they probably were just trying to hide their own shortcomings.

We will have to see Panther Cove to see did they screw up again.

 

[jur]

The P core team sold the idea they can make a better and denser core with killing HT and the development time would be faster without security issues.

This may be true to an extent. Also, they did other optimizations. Shared L2 cache and without HT they can run slightly higher clocks. I don't think they would share L2 cache, if there was HT, since L2 would have to serve 4 threads.

 

[LightningZ71]

The sad part is, as far as the rumors go, that Lion Cove retained all of the circuitry needed for HT, so it was bigger than it needed to be while still not really setting the world on fire in ST performance.

In my personal opinion, they chose the opposite strategy than was needed and should have instead optimized the E cores for SMT as they would be running lower clocks deep in the efficiency area of the v/f curve and completely gone all out on ST performance for the P cores.

The problem there is that they shared those cores with their server products and didn't have the resources to design a third unique core.

 

[regen1]

Here the Sr. PE is referring to roughly 15% for SMT(may be just for demonstration). May be for Lion Cove it is above 10% area trade off. Claims the cores are more area efficient due to removal of SMT. It's not just security issues, changes to security engine, validation time, slightly lower peak ST but also the core design has significant changes.
SMT is generally a great benefit per area but it is not an universal gain in performance. Most HPC workloads don't prefer it.

Once it was removed from client, streamlining the development instead of developing 2 different P-core designs one for client(without SMT) and one for server(with SMT) made sense.

For AMD designs SMT is good. Dense and Classic versions of Zen cores are similar in architecture unlike Intel's P & E cores.
CCDs are much smaller and they stitch more of them for server. On Intel's side they are stitching very large compute dies. Intel's server SKUs' margins and BoM are quite bad relatively. They still have a lot of other issues to solve with its P-cores, L3.

With unified core they can then look to having it back with lesser complications which is perhaps what they might do but even then many of the SMT's trade-offs remain. Core-counts are going to increase further with Coral Rapids/Zen7. Initial DMR was up to 192 cores which was increased to 256.

 

[regen1]

Have you wonder why PTL, CWF and DMR (NVL also) all come without HT under leadership of Pat? Everyone knows HT is improving MT performance by increasing 5% of die area only and yet. Hoho, the same for ditching AVX-512 and then bring it back...

Well, Lunarlake and Arrowlake too don't have HT.
Since you are citing CWF, which E-cores till date either in client or server from Intel has had HT?

And how would they have AVX512 in client when E-cores didn't have the support for it . Add to that Windows doesn't support 2 different core designs with different instruction sets even though Linux can.

 

[OneEng2]

Tks, I have changed the percentage. My question remains: why does Pat ditch HT which will greatly improve performance of MT?

I believe the thought was the transistor budget was needed to improve ST performance. Also, SMT adds a great deal of complexity to the design.

I disagree.

In DC SMT pays off to the tune of about 40%. DC is the land of milk and honey... And profit margins. Intel made a strategic mistake IMO.

 

[511]

In DC SMT pays off to the tune of about 40%. DC is the land of milk and honey... And profit margins. Intel made a strategic mistake IMO.

it's not 40% vs a ST focused core you can clock your cores a bit higher if you disable SMT in Intel's case lets by killing SMT i can clock by 5-10% and i have used the area to increase ST resources so i have like 5% more ST performance.
These are hypothetical numbers but it is possible to do so and turning off HT increases core clock.

 

[OneEng2]

it's not 40% vs a ST focused core you can clock your cores a bit higher if you disable SMT in Intel's case lets by killing SMT i can clock by 5-10% and i have used the area to increase ST resources so i have like 5% more ST performance.
These are hypothetical numbers but it is possible to do so and turning off HT increases core clock.

In Intel's OLD case. AMD have shown it is possible to have SMT have a very minor impact on power.

Regardless, even if enabling SMT docked the processor 10%, the 40% MT improvement would more than justify the architecture.

I don't know the die space penalty for a full AVX 512 path, but I suspect the same is true here... For AVX loads.

 

[511]

In Intel's OLD case. AMD have shown it is possible to have SMT have a very minor impact on power.

Regardless, even if enabling SMT docked the processor 10%, the 40% MT improvement would more than justify the architecture.

I don't know the die space penalty for a full AVX 512 path, but I suspect the same is true here... For AVX loads.

I have an RWC and I tested it with and without quiet a while back I can test it again if you want reference I can disable the E cores and run cinebench.
Which cinench version to use r15/r23?
I will set the power limit to 45W🙂.

 

[coercitiv]

Here the Sr. PE is referring to roughly 15% for SMT(may be just for demonstration). May be for Lion Cove it is above 10% area trade off. Claims the cores are more area efficient due to removal of SMT.

Intel made a number of claims with the launch of Lunar Lake that outlined both performance and area cost of their SMT implementation. Assuming their performance and perf/area claims were accurate, we could even estimate SMT area cost at around 10%:

So according to Intel, performance improves by ~30% when using SMT. At the same time removing SMT logic results in only a 15% perf/area loss, so the SMT core has about 17.5% better perf/area. This means the SMT enabled core is ~10.5% larger.

If we take these numbers at face value, it seems AMD managed to yield more out of SMT in terms of perf/area. My fully speculative opinion on this is their design teams focused on improving SMT efficiency over the years, while Intel did less in that regard. AMD leaned into SMT, Intel walked away from it. One could even entertain the thought that Intel's claims about SMT are a bit of a self-fulfilling prophecy.

 

[511]

It's coming back with Coral Rapids though in 2028-29 xDd customer must be complaining that we get the Same vCPU count even though the performance is doubled

 

[OneEng2]

If we take these numbers at face value, it seems AMD managed to yield more out of SMT in terms of perf/area. My fully speculative opinion on this is their design teams focused on improving SMT efficiency over the years, while Intel did less in that regard. AMD leaned into SMT, Intel walked away from it. One could even entertain the thought that Intel's claims about SMT are a bit of a self-fulfilling prophecy.

AMD claims 5% extra die space and gets ~ 40% in DC from SMT. Intel's implementation appears to be both fatter, and less capable.

I'm not sure that it is a simple matter for Intel though. I think that it takes a complete core re-work with the idea of SMT being integral to all design aspects of the core. I don't think it is something that Intel can just slap onto an existing design.

This same logic goes for chiplet design. I think it takes more than simply taking part of the schematic and putting it on a different die. I think that the overall architecture must revolve around that relatively high latency interface and core designers need to mitigate the issues through design decisions throughout the core.

It's coming back with Coral Rapids though in 2028-29 xDd customer must be complaining that we get the Same vCPU count even though the performance is doubled

I think what DC customers are complaining about is the relative lack of performance of Intel's DC lineup. In DC, overall performance pays for itself many times over for the customer.

 

[511]

AMD claims 5% extra die space and gets ~ 40% in DC from SMT. Intel's implementation appears to be both fatter, and less capable.

the 40% is from where it was around 30% iirc

I think what DC customers are complaining about is the relative lack of performance of Intel's DC lineup. In DC, overall performance pays for itself many times over for the customer.

I mean with GNR the performance is there but it's not class leading in all benchmarks and neither is AMD's but AMD has more wins in benches than GNR