Discussion Intel Nova Lake in H2-2026: Discussion Threads

[511]

Which means devs will need to make binaries just for APX processors (not many will) or let Intel dynamically recompile their binaries (insane).

Exactly this part is insane like unbelievable

 

[gdansk]

Yes it requires recompile either way. 🤣 Modern game devs don't even want to use x86_64_V3 man that is haswell level ISA.

And if they recompile with REX2 prefix, how will Zen or Arrow Lake, Raptor Lake, or Sky Lake processors run the code?
And considering the install base, why would devs make an APX build? Even if NVL is wildly successful there's very little reason to target APX. So I understand that Intel could actually be planning this. But I'm not gonna run their software even if I do end up with an NVL processor.

 

[igor_kavinski]

or let Intel dynamically recompile their binaries (insane).

That's the Intel we know and love

Heck, I hope they brute-force some AVX2 to AVX10.2 code conversion too.

 

[511]

And if they recompile with REX2 prefix, how will Zen or Arrow Lake, Raptor Lake, or Sky Lake processors run the code?
And considering the install base, why would devs make an APX build? Even if NVL is wildly successful there's very little reason to target APX. So I understand that Intel could actually be planning this. But I'm not gonna run their software even if I do end up with an NVL processor.

Bruh x86_64_V3 is Haswell ISA

 

[gdansk]

Bruh x86_64_V3 is Haswell ISA

I am still talking about APX. But it's the same argument shifted a decade. In the Windows world, where they ship binaries instead of code, software usually targets the common denominator. For an example of why, look for the Steam threads complaining about nearly any game with an AVX requirement.

 

[511]

I am still talking about APX. But it's the same argument shifted a decade. In the Windows world, where they ship binaries instead of code, software usually targets the common denominator. For an example of why, look for the Steam threads complaining about nearly any game with an AVX requirement.

Yeah but at some point we have to drop those users otherwise we will be stuck AVX should be mandatory at this point this is something ARM camp doesn't worry about lol.
TVs and Cheap devices are 32 bit and Rest are 64 but Android studio does the binary heavy lifting for 99% of the app

 

[Thunder 57]

Yes it requires recompile either way. 🤣 Modern game devs don't even want to use x86_64_V3 man that is haswell level ISA.

If that's true it should change. AVX2 has been around for a long time and along with AVX I'm sure could provide a decent boost. Intel being Intel though segmented it for awhile so it was i3 and above. Looks like that's coming back to bite them in a small way.

Also, with games like the next CoD and BF requiring TPM 2 and Secureboot the minimum processor just got a lot newer. I'd bet those games make use of AVX/AVX 2 and then Steam users will be bitching about TPM instead of AVX .

 

[gdansk]

this is something ARM camp doesn't worry about lol.

If they take over the Windows market, they will have the same problem going forward. New ISA features will take forever to trickle down and applications will target the common denominator.

 

[511]

If they take over the Windows market, they will have the same problem going forward. New ISA features will take forever to trickle down and applications will target the common denominator.

Only Apple gets by this.

 

[poke01]

Only Apple gets by this.

Even Apple had Rosetta 2 and they will be removing it in the next 2 years. That’s 6-7 years of x86 translation. They also state a substate of Rosetta2 will remain for older games that use Intel libraries after macOS 27.


Going back to Nova lake leak, Nova Lake AX memory is MoP is interesting after OEMs didn’t like MoP Lunar Lake.

A 20% 1t uplift is good, let’s see if it pans out.

 

[511]

Going back to Nova lake leak, Nova Lake AX memory is MoP is interesting after OEMs didn’t like MoP Lunar Lake.

it is due to complex signaling which is a pain on PCB AMD has signaling issues on Halo beyond DDR5-8000 so it's basically a way to mitigate that and they can do 10667 DDR5 with MoP also they are taking headache from OEMs it's a double win i don't know for margin though.

Intel is the one who doesn't like MoP due to its packing cost.

 

[Joe NYC]

Going back to Nova lake leak, Nova Lake AX memory is MoP is interesting after OEMs didn’t like MoP Lunar Lake.

That's just Urban Legend that everyone keeps repeating.

Lunar Lake has MoP and has 47 unique laptop models currently for sale.
Strix Halo does not have MoP and has 1 laptop for sale.

It's just too bad AMD fell for it and is now holding the bag.

 

[Thunder 57]

That's just Urban Legend that everyone keeps repeating.

Lunar Lake has MoP and has 47 unique laptop models currently for sale.
Strix Halo does not have MoP and has 1 laptop for sale.

It's just too bad AMD fell for it and is now holding the bag.

Intel still has a lot of power in the mobile market. It's too bad though as it means Medusa Halo is probably done. They may be able to use some of their knowledge (IOD) in future designs though.

 

[dangerman1337]

Per MLID:
View attachment 128488

Two compute tiles on TSMC N2P with large amounts of L3 cache to compete against AMD's V-cache. Talk about brute force.

Doesn't look cheap and I do wonder why for bLLC variants Intel decided to do 8+16 than something like 12P Cores with more cache, 192MB would've been sweet per compute tile.

Though conceivably you can get NVL/RZL and then upgrade to a eLLC HML circa 2030/2031 when it goes on sale. I wonder if Intel with bLLC/eLLC will sell them day one of launching the architecture than spacing it out like AMD has done with X3D (kinda of silly when X3D is a top seller). 2028+ which is like many years of Intel experimenting with attempts with additional cache finally comes to fruition.

 

[Joe NYC]

Intel still has a lot of power in the mobile market. It's too bad though as it means Medusa Halo is probably done. They may be able to use some of their knowledge (IOD) in future designs though.

Do you mean done as in design complete or done as in finished (in the marketplace) even before it is rolled out?

It seems there will be 2 versions of Medusa Halo, one with Strix Halo IOD and LPDD5 and 2nd with new RDNA5 IOD with LPDDR6. The second one is likely still under development, and will likely be compete (and lose) to Nova Lake Halo in graphics workstation laptop market. in 2027.

Because the sadomasochims between AMD and OEMs, AMD trying to inflict pain on them to design multiple challenging mobo layouts, and OEMs in return saying "screw this, shove your Medusa up all your multiple incompatible notebook sockets" will continue until the morale improves.

 

[msj10]

Doesn't look cheap and I do wonder why for bLLC variants Intel decided to do 8+16 than something like 12P Cores with more cache, 192MB would've been sweet per compute tile.

There will be no pure P core tiles just forget it.
even when the Unified Core comes out they will probably still have hybrid with classic/dense setup.

 

[dangerman1337]

There will be no pure P core tiles just forget it.
even when the Unified Core comes out they will probably still have hybrid with classic/dense setup.

I think the point of Unified Core for Desktop is just one core for the Compute tiles with LPE cores in the IOD. Just like AMD is planning with Zen 6 and onwards.

 

[Thunder 57]

Do you mean done as in design complete or done as in finished (in the marketplace) even before it is rolled out?

It seems there will be 2 versions of Medusa Halo, one with Strix Halo IOD and LPDD5 and 2nd with new RDNA5 IOD with LPDDR6. The second one is likely still under development, and will likely be compete (and lose) to Nova Lake Halo in graphics workstation laptop market. in 2027.

Because the sadomasochims between AMD and OEMs, AMD trying to inflict pain on them to design multiple challenging mobo layouts, and OEMs in return saying "screw this, shove your Medusa up all your multiple incompatible notebook sockets" will continue until the morale improves.

Done as in finished. It'd be nice to be wrong though.

 

[511]

Because the sadomasochims between AMD and OEMs, AMD trying to inflict pain on them to design multiple challenging mobo layouts, and OEMs in return saying "screw this, shove your Medusa up all your multiple incompatible notebook sockets" will continue until the morale improves.

That's the whole point of MoP in NVL-HX

 

[branch_suggestion]

It seems there will be 2 versions of Medusa Halo, one with Strix Halo IOD and LPDD5 and 2nd with new RDNA5 IOD with LPDDR6.

Still hard to say, regardless Medusa is the same socket and uses the same soldered mobos.

The second one is likely still under development, and will likely be compete (and lose) to Nova Lake Halo in graphics workstation laptop market. in 2027.

NVL-AX does not have a hope of beating full fat Medusa Halo at any workload.
Now the version with a mildly refreshed Strix Halo SoC die, sure, still loses in CPU workloads due to power constraints.

Because the sadomasochims between AMD and OEMs, AMD trying to inflict pain on them to design multiple challenging mobo layouts, and OEMs in return saying "screw this, shove your Medusa up all your multiple incompatible notebook sockets" will continue until the morale improves.

I mean Intel has quite a few different sockets and associated mobo configs but AMD must be doing something specifically wrong by not doing MoP.
Or maybe comparing LNL which is a familiar paradigm in a higher volume market should not be compared to a whole new swimlane?

 

[511]

NVL-AX does not have a hope of beating full fat Medusa Halo at any workload.
Now the version with a mildly refreshed Strix Halo SoC die, sure, still loses in CPU workloads due to power constraints.

The 512 EU Version has if it launches the 384 EU Version don't for sure

 

[branch_suggestion]

The 512 EU Version has if it launches the 384 EU Version don't for sure

Perhaps, but can it do that in a tablet/T&L form factor like Strix Halo can?

 

[MS_AT]

Exactly this part is insane like unbelievable

If they would target only scalar code (APX) it at least seems doable. Diassemble the binary on first run, find all the stack push/pop and spills, replace if possible with additional registers, compile back. That at least seems managable if the calling conventions remian unchanged. It would be insane if they wanted to rewrite to AVX10. Still seems like a headache, on the other hand otherwise it will be unused for years to come.

If that's true it should change. AVX2 has been around for a long time and along with AVX I'm sure could provide a decent boost.

You can find petitions online from people to turn off AVX2 in games that are using it. Since they want to hold on Nehalem CPUs they pair with 3090 or 4090

Although for game usage I would expect AVX512 would be is easier to use due to predicated instructions. The obvious problem is availability

 

[511]

At least the server won't be stuck with old mindset unlike consumer

 

[511]

Perhaps, but can it do that in a tablet/T&L form factor like Strix Halo can?

It can tbh it's weird though TSMC CPU Tile and Intel iGPU Tile