Discussion Intel Nova Lake in H2-2026: Discussion Threads

[dullard]

Exactly, it's the hybrid bonding that's the sticking point.

Conceptual simplification of EMIB and Foveros 2.5D is that they're the same as normal FCBGA packaging, just using a silicon substrate instead of an organic substrate. Using silicon enables the finer pitch both because of matched thermal expansion coefficient and the relative ease of making fine wires/pads on silicon. But it's still a solder connection between the pads.

Foveros direct requires getting the two die perfectly flat and aligned such that the pressure/heat of the process bonds copper to copper and dielectric to dielectric. If there's any gaps in that bond electromigration can occur and you'll have raptor lake * 100. Which is again more of a problem with Intel's design because they have all the power hungry core logic on top rather than the power sipping cache.

That and their EMIB packaging fabs were not ready.

Fab 52 in Arizona was declared open on Oct 9, 2025 (less than 2 months ago). https://www.techpowerup.com/341531/...-in-arizona-panther-lake-reveal-set-for-oct-9

And their Pelican Fab in Malaysia is nearing completion: https://www.techpowerup.com/343545/...n-malaysia-packaging-fab-for-emib-and-foveros

Correct me if I'm wrong, but I thought all other EMIB was done in their research facility which is small scale with low yields.

 

[Khato]

Correct me if I'm wrong, but I thought all other EMIB was done in their research facility which is small scale with low yields.

It's fab 9/11X in Rio Rancho New Mexico that currently handle all the advanced packaging production.

The Oregon R&D facilities can also chip in of course. I wouldn't exactly call those facilities 'small scale' though - they just typically aren't relied on for mass production as such would be detrimental to continued process development. Same goes for their yield - it's usually considered 'low' just because they're the ones that iterate though revisions to get the base 'recipe' down to where it's acceptable for high volume manufacturing. They could continue from that point, but instead they'll move on to whatever's next.

 

[dullard]

The Oregon R&D facilities can also chip in of course. I wouldn't exactly call those facilities 'small scale' though - they just typically aren't relied on for mass production as such would be detrimental to continued process development.

Small scale: as in not enough to meet demand. Intel just partnered with Amkor to help do more EMIB production. https://www.techpowerup.com/343510/intel-and-amkor-team-up-to-scale-emib-packaging-production

 

[Khato]

Small scale: as in not enough to meet demand. Intel just partnered with Amkor to help do more EMIB production. https://www.techpowerup.com/343510/intel-and-amkor-team-up-to-scale-emib-packaging-production

Fair enough.

Yeah, Intel easily has enough advanced packaging capacity to cover their own products in Fab 9/11X. And I believe that the Malaysia facility is going to be 1.5-2x the capacity? But even that apparently isn't adequate now that TSMC's capacity constraint forced their customers to take a look at what Intel had to offer... and realize that they've been fools for not doing so earlier.

Edit: I forgot to mention that NVIDIA's early issues with CoWoS-L are likely another factor that makes Intel's well-proven EMIB a more attractive alternative.

 

[DavidC1]

Half this forum thinks 18A won't have any volume because they are cutting capex.
So which is it, is there not enough volume for 18A that they can't use it on all their highest margin parts, or is it that they have to find products to fill out the 18A fabs?

That's what happens at a company level. We talk like Intel is one person, where it's made of multiple people, and on top of that the infighting that has existed since Andy Grove days(which I argue he started the whole culture) and has worsened is reaching a zenith point.

They made bad decisions and contradictory decisions, due to them changing CEOs like Rome changed emperors when the empire was declining.

It does NOT change from the fact that Foundry is all-in or nothing.

Well it won't be zero, tons of other stuff is being fabbed on 18A.

? Not having Clearwater would be a significant loss. Every Intel part that is external is revenue 0 for Intel Foundry. I can't see why I'm even discussing this. They should be almost forced to move everything to Intel Foundry except for the halo parts. Heck, US government and Nvidia should force this. Every investors should.

Who was arguing this lol

That's what arguing on cost per die implies - that Intel and AMD are the same, when one has a foundry and other relies on one. They are not comparable.

By going TSMC, Clearwater would be on time, not delayed. It'll be 1Q-2Q early and have better ramp up.
How much will the delay cost? Who knows...
But yeah, intel has gone so deep in foundry that make it have no choice.

That's why it don't matter. 1Q-2Q delay would look like nothing when the losses on the Foundry side is consistently showing nearly $10 billion. If they were abandoning Foundry, then sure. This is all-in or nothing, no middle ground.

This started based on Gelsinger's plan that he could use external as a Stick to process team that "if you don't meet expectations" they can get penalized by the design team not using them, and over long time benefitting Intel because they would be motivated not to be rendered irrelevant and kicked out. It would be a short lived thing where over longer periods of time theoretically you'd have a strong design and strong process team. Of course that didn't pan out as expected, because Intel's problems are way bigger than even he knew.

I fully understand that you're an Intel foot soldier but please be reasonable: since when marketing slides of any company are unquestionable truth?

Btw, on this slide you've clearly missed Intel famous "up to" phrase which means that 17/30 percent is best case scenario.

It actually means nothing. We had upto's before and it turned out to be rather more of an average. And we had upto's before where it couldn't even meet the numbers in the most optimistic scenario.

With Intel you have one side saying X and the other side is saying Y, all the time.

 

[511]

Exactly, it's the hybrid bonding that's the sticking point.

Conceptual simplification of EMIB and Foveros 2.5D is that they're the same as normal FCBGA packaging, just using a silicon substrate instead of an organic substrate. Using silicon enables the finer pitch both because of matched thermal expansion coefficient and the relative ease of making fine wires/pads on silicon. But it's still a solder connection between the pads.

EMIB is different flow than Foveros-S

Foveros direct requires getting the two die perfectly flat and aligned such that the pressure/heat of the process bonds copper to copper and dielectric to dielectric. If there's any gaps in that bond electromigration can occur and you'll have raptor lake * 100. Which is again more of a problem with Intel's design because they have all the power hungry core logic on top rather than the power sipping cache.

Yeah

 

[QuickyDuck]

Like what I have said. TSMC is the master of hybrid bonding. They could go TSMC and make the job done.
Anyway, the decision had been made and there's also politics involved.

 

[Khato]

Like what I have said. TSMC is the master of hybrid bonding. They could go TSMC and make the job done.
Anyway, the decision had been made and there's also politics involved.

How many designs make use of TSMC hybrid bonding?

 

[511]

That's what happens at a company level. We talk like Intel is one person, where it's made of multiple people, and on top of that the infighting that has existed since Andy Grove days(which I argue he started the whole culture) and has worsened is reaching a zenith point.

They made bad decisions and contradictory decisions, due to them changing CEOs like Rome changed emperors when the empire was declining.

Intel forgot the most crucial points of Andy Grove after him leaving tbh like "only the paranoid survive" and pivoting your business "strategic inflection point" the past 15-20 years leadership has been a clown show

 

[regen1]

Leaving Intel

Leaving Intel

www.brendangregg.com

 

[Joe NYC]

It's that much worse for Intel because they're not just putting some extra cache on top, aka attaching two die together. They're attaching 3 compute die to an active base die. An 80% success rate for each attachment yields 80% success with AMD's simple approach... and roughly 50% success with CWF.

Intel did set the bar quite high for the first implementation of hybrid bond.

Perhaps the thinking was that server can absorb some yield losses better and the volume of these server chips will start quite small. Which are both valid assumptions.

Still, starting from the simplest possible (one on one) stacking would have been more straight forward approach to learn and perfect the process...

 

[LightningZ71]

Server also offers a lot of recovery options. If one of the three compute does fails, the other two can be used in lower SKUs.

 

[Khato]

Unfortunately binning only works if the failure occurs during testing. If it happens after the part has been running for a few weeks in a server you then have a very grumpy customer.

Electromigration makes it far easier to produce a reliable hybrid bond that has high signal density with very low power requirements (AMD) than high signal density with high power requirements (Intel.) Pretty sure that's the reason why there haven't been any other customers using TSMC's hybrid bonding as of yet? Would like to be wrong on that, but didn't come up with anything in brief searching, nor have I recalled reading about any.

 

[Joe NYC]

Unfortunately binning only works if the failure occurs during testing. If it happens after the part has been running for a few weeks in a server you then have a very grumpy customer.

Electromigration makes it far easier to produce a reliable hybrid bond that has high signal density with very low power requirements (AMD) than high signal density with high power requirements (Intel.) Pretty sure that's the reason why there haven't been any other customers using TSMC's hybrid bonding as of yet? Would like to be wrong on that, but didn't come up with anything in brief searching, nor have I recalled reading about any.

The new Zen 5 3D stacking now also passes through power to the cores, so higher power requirements than prior 3D stacking method when only the SRAM cache was on top of the chip.

But the power could be split between a number of TSVs (a number of hybrid bonds) or they can design thicker TSVs with larger contact area for power delivery.

The same would apply to Clearwater Forest.

 

[Fjodor2001]

So Panther Lake will be officially launched on 5 January at CES 2026.

Is there any chance we’ll get some teaser info about Nova Lake too?

 

[Hulk]

So Panther Lake will be officially launched on 5 January at CES 2026.

Is there any chance we’ll get some teaser info about Nova Lake too?

I suspect we will see some running Nova Lake specimens but with very little details presented.

But we will know everything about the new P and E cores that will be in both Panther and Nova Lake and that will tell us quite a bit about Nova Lake.

 

[511]

I suspect we will see some running Nova Lake specimens but with very little details presented.

But we will know everything about the new P and E cores that will be in both Panther and Nova Lake and that will tell us quite a bit about Nova Lake.

NVL Core's and ISA has already been officially published in the ISA Manual

 

[Hulk]

NVL Core's and ISA has already been officially published in the ISA Manual

I'm currently more interested in various benchmark scores and application performance as well as frequencies during the runs and power usage.

 

[511]

I doubt power would be a problem unless Intel pulls an Intel and do GHz go brr node with design.

 

[DavidC1]

But we will know everything about the new P and E cores that will be in both Panther and Nova Lake and that will tell us quite a bit about Nova Lake.

Not really. Arctic Wolf for example will likely be the 12-wide x86 core that Jim Keller was working on. 12-wide issue by itself will only bring few single digit % gains. So that's just an enabler. Other than that, we don't know anything about it. Ticks like Darkmont we can speculate much easier. How much of Skymont could we have got from Gracemont and Crestmont? Nothing really.

NVL Core's and ISA has already been officially published in the ISA Manual

Yes, but we don't know much beyond that.

Prescott and Conroe share the same ISA too. The architecture itself is quite different however.

 

[511]

Not really. Arctic Wolf for example will likely be the 12-wide x86 core that Jim Keller was working on. 12-wide issue by itself will only bring few single digit % gains. So that's just an enabler. Other than that, we don't know anything about it. Ticks like Darkmont we can speculate much easier. How much of Skymont could we have got from Gracemont and Crestmont? Nothing really.

Arctic wolf is post Jim Keller it's lead by Stephen Robinson

 

[MS_AT]

How much of Skymont could we have got from Gracemont and Crestmont? Nothing really.

A lot? Isn't it just more of the same? Or are you able to name at least 3 distinct features which are not about making something bigger? (Clustered decode was there, it just got bigger, distributed schedulers were there, got bigger, more of execution units, bigger BTB and reorder buffer). Actually from memory, I think only Nanocode stands out as something that is new, and not just bigger. Of course might be wrong.

 

[Hulk]

Not really. Arctic Wolf for example will likely be the 12-wide x86 core that Jim Keller was working on. 12-wide issue by itself will only bring few single digit % gains. So that's just an enabler. Other than that, we don't know anything about it. Ticks like Darkmont we can speculate much easier. How much of Skymont could we have got from Gracemont and Crestmont? Nothing really.

Yes, but we don't know much beyond that.

Prescott and Conroe share the same ISA too. The architecture itself is quite different however.

My mistake, I thought Panther and Nova Lake were sharing core architecture. This is great news, two new architecture releases in the same year from Intel!

I was under the impression the changes from Panther to Nova cores would be quite minimal, glad I was wrong!

 

[511]

I was under the impression the changes from Panther to Nova cores would be quite minimal, glad I was wrong!

both are a Tock the P Cores have been leaked to have shared L2 of 4 MB between 2 P Cores also it might be due to panther lake and panther cove the code name for P cores in DMR

 

[Hulk]

both are a Tock the P Cores have been leaked to have shared L2 of 4 MB between 2 P Cores also it might be due to panther lake and panther cove the code name for P cores in DMR

Wow, this is an aggressive path for Intel to be releasing basically 4 new core architectures inside of 12 months, if all goes well I wish them luck.