Discussion Intel Nova Lake in H2-2026: Discussion Threads

[Keysplayr]

In Cinebench. Why extrapolate, repeatedly, from one single benchmark chart that doesn't represent your workload?

If you expand the benchmark scope what happens? Where does Arrow Lake fall apart? Where does scaling fall apart in general? Not in Cinebench.

It doesn't really. It's a fast architecture but lacks in gaming compared to the 14th gen. Other than that, it's quite a good arch. Nice and cool. Lots of cores. No hyperthreading (which I like, I don't really know why. HT felt fake.) Keep in mind, I said lacks in gaming but this doesn't mean it's bad in gaming by any means. Just in benches it has lower numbers but those numbers are still just fine.

 

[LightningZ71]

It feels like Arrow Lake H would have been better with only 4 Lion Cove cores and 16 Skymont cores, but with the Skymont cores limited to about 500Mhz less frequency. Bringing them back into a more optimum VF curve range would have fell helped immensely. They are pushing freq and blowing out power to keep up with their competition. It's also not like their Lion Cove cores are THAT much higher in IPC than their Skymont cores.

 

[OneEng2]

Yeah but the Cache latency is not the same as for node Delta it's N3B it's not a full node better than N4P at best single digit difference.

N3B is a full node shrink below N4P IMO.... more so than N3E. The reason it wasn't popular is that it is expensive, not because it isn't good. N3E relaxed the performance some, but the cost alot.

NVL on N2 vs Zen 6 on N2 will be interesting for sure. First time that I can recall that Intel and AMD will have products on the same node to compare with.

 

[reaperrr3]

N3B is a full node shrink below N4P IMO.... more so than N3E. The reason it wasn't popular is that it is expensive, not because it isn't good. N3E relaxed the performance some, but the cost alot.

Are you sure?

From TSMC's own numbers, it rather looks like N3E relaxes the density, but actually performs slightly better vs. N3(B).
Might just be random marketing, but TSMC's own official numbers were

+15% perf or -30% power for N3
+17%/-32% for N3E

The only thing I don't know for sure is if N3B was a pure yield fix, or upgrade similar to what N3P is for N3E.

 

[jpiniero]

From TSMC's own numbers, it rather looks like N3E relaxes the density, but actually performs slightly better vs. N3(B).

Yes

 

[Joe NYC]

Are you sure?

From TSMC's own numbers, it rather looks like N3E relaxes the density, but actually performs slightly better vs. N3(B).
Might just be random marketing, but TSMC's own official numbers were

+15% perf or -30% power for N3
+17%/-32% for N3E

The only thing I don't know for sure is if N3B was a pure yield fix, or upgrade similar to what N3P is for N3E.

Didn't N3E also lower the density slightly?

 

[adroc_thurston]

Didn't N3E also lower the density slightly?

it did.

 

[LightningZ71]

IIRC, logic density between both was nearly identical. SRAM density was the difference. N3B had a slight shrink to the SRAM arrays, but it caused parametric yield issues. N3E went back to the N4P macro, but left the rest of the logic the same as N3B. Again. Just working from memory early in the morning.

 

[511]

IIRC, logic density between both was nearly identical. SRAM density was the difference. N3B had a slight shrink to the SRAM arrays, but it caused parametric yield issues. N3E went back to the N4P macro, but left the rest of the logic the same as N3B. Again. Just working from memory early in the morning.

Nope N3B is 1.04 denser than N3E. N3B sucked ass cause it got delayed and the PPA was nothing to write home about for HPC not to mention it was too expensive

 

[LightningZ71]

Well yes. 6 extra layers and several instances of EUV double patterning will do that to you. 1.04 density difference isn't anything to write home about for density, but it's notable that (according to the graphics in AT's articles) the SRAM cell size is exactly the same size as N5.

 

[511]

The SRAM Cell is roughly 0.199 N3B vs 0.210 for N5/3/2 and 18A/AP.

 

[adroc_thurston]

The SRAM Cell is roughly 0.199 N3B

Did anyone ship .199 N3b cell?

 

[511]

Did anyone ship .199 N3b cell?

🍎

 

[adroc_thurston]

🍎

Techinsights said the opposite.

 

[511]

Don't have access to Tech insights xDd. Tech insight also said 171mxtor/mm2 for N5🤣🤣

 

[Doug S]

Did anyone ship .199 N3b cell?

Apple & Intel. They're the only ones who used N3B.

 

[511]

Apple & Intel. They're the only ones who used N3B.

Just cause they used N3B doesn't mean they used 0.199 bitcell in the YT video they have a teardown.

 

[Fjodor2001]

(Almost) Regardless of how NVL-S will perform I'm very excited about it from a purely technological standpoint. Because so much will be changed/added.

I tried to assemble a list of everything that will be new/changed compared to previous CPU generation (ARL-S):

Process tech: TSMC N3B/N5P/N6 => TSMC N2 + Intel 18A
CPU: 8P+16E (=24C) => 16P+32E+4LPE (=52C)
CPU uArch: Lion Cove (P) + Skymont (E) => Coyote Cove (P) + Arctic Wolf (E)
CPU uncore: Unsure about this. Does anyone know what changes are expected?
RAM speed: DDR5 6400 => DDR5 8000
iGPU: Xe-LPG; 4 Xe-cores; 64 EU => Xe3; Unknown core/EU count
NPU: NPU3 (13TOPS) => NPU4 (48 TOPS)
PCIe: CPU: 20xPCIe 5.0 + 4xPCIe4; Chipset (Z890): 24xPCIe 4.0 => CPU: 24xPCIe 5.0; Chipset (?): 8xPCIe 5.0 + 16xPCIe 4.0
TDP: 125W => 150W (and yes, much higher at peaks for both)
Anything else: ?

I'm sure I missed or specified something wrong. If so, please feel free to add and/or correct.

Anyway, a lot of new tech. The only worry is that that for some of the changes it'll be hard to evaluate how much impact each change has on performance, since so many things are changed in parallel.

 

[dullard]

Anything else: ?

1) It is hinted at in your post, but all CPUs get a decent increase in core counts.

I think the biggest bump for most people will be that the Ultra 5 (i5) class gets a nice core increase. For example, the top Ultra 5 goes from 6P + 8E (14 threads) to 8P + 16E + 4 LPE (28 threads). Doubling the thread count is nothing to scoff at--especially for these mid range CPUs that so many businesses are built around. I've seen some claims that the i5 is Intel's best selling line, so this is actually significant.

2) The return of the Ultra 3 (i3). Yes, technically Arrow Lake now has a single Ultra 3 CPU, but it launched much later and is pretty underpowered. Even that lowly Ultra 3 is going from 4P + 4E (8 threads) to 4P + 8E + 4 LPE (16 threads) which is a massive bump for the CPUs that do really need the bump. But also there will now be multiple Ultra 3 chips to choose from.

3) The addition of LP-E cores (and making them both more powerful and double in count) means that the LP-E cores should have a functional low power state when running basic tasks (internet browsing, media streaming, etc). The LP-E cores were too few and too weak to run well in the past Intel chips.

4) Slight change: The 150 W TDP is only for the top two Nova Lake chips.

5) LGA1954 socket.

6) Add to your GPU line: it will have the XE4 display engine.

7) Rumors of a bLLC (big last level cache) on some CPUs.

 

[511]

The Display and Media IP is Xe4 while the GPU IP is Xe3P also waste of die unit is 75 TOPS for NVL. Integrated TB 5 with retimers and PD.

 

[igor_kavinski]

5) LGA1954 socket.

The first long lived Intel socket? Can't wait to see how Intel messes this up with incompatibilities and prevents the launch mobos from accepting the 4th gen CPUs on the same socket. I mean, by some miracle maybe they replicate AMD's success with AM4 but you don't see many miracles from Intel these days.

 

[511]

The first long lived Intel socket? Can't wait to see how Intel messes this up with incompatibilities and prevents the launch mobos from accepting the 4th gen CPUs on the same socket. I mean, by some miracle maybe they replicate AMD's success with AM4 but you don't see many miracles from Intel these days.

Plot twist LGA-1851 was supposed to be 3 gen socket with MTL/ARL/PTL

 

[ToTTenTranz]

The Display and Media IP is Xe4 while the GPU IP is Xe3P also waste of die unit is 75 TOPS for NVL. Integrated TB 5 with retimers and PD.

Integrated TB5 is actually pretty awesome, as it'll allow for asymmetric 40/120Gbps transfer rates which should virtually nullify all the eGPU connection overhead.
Current solutions with external controllers use 4x lanes PCIe4 that are limited to 64Gbps duplex.

 

[511]

Integrated TB5 is actually pretty awesome, as it'll allow for asymmetric 40/120Gbps transfer rates which should virtually nullify all the eGPU connection overhead.
Current solutions with external controllers use 4x lanes PCIe4 that are limited to 64Gbps duplex.

Yup it will be especially good on Mobile and OEMs will find a way to gimp this

 

[511]

On the Topic of NVL Arctic Wolf vs Coyote Cove which will have higher perf/clock what do you guys think?