Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15W?Intel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz?5 GHz4.8 GHz
L3 Cache12 MB12 MB12 MB
TDP15 - 55 W15 W ?17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB32 GB128 GB
Bandwidth136 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz?2 GHz2.5 GHz
NPUGNA 3.018 TOPS48 TOPS49 TOPS






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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Last edited:

Hulk

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I’m referring more about the LPE cores. They’re significantly more performant per watt.
The E cores have to get quite a bit more juice just to perform at the same level or slightly better. Which is odd because the LPE cores are just slightly down-clocked Darkmonts. Yet they have a very different profile.
Oh okay. Yes, I noticed that as well.
I can't explain it. Why would Darkmont LPE be significantly more power efficient than Darkmont E?
 

Hulk

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Cause they are not on Ring so they have different power profile.
I'm not following? What difference specifically make a Darkmont LPE core use about 1 watt less than a Darkmont E core at the same work rate (performance)? A difference like that would seem to indicate a different architecture, node, or both? At first I was thinking super low leakage silicon that doesn't clock high but is very power efficient?

Thing is the LPE's are on the N6 process platform controller tile, which you would think would be less power efficient?

I'm all confused now.
 

511

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Jul 12, 2024
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I'm not following? What difference specifically make a Darkmont LPE core use about 1 watt less than a Darkmont E core at the same work rate (performance)? A difference like that would seem to indicate a different architecture, node, or both? At first I was thinking super low leakage silicon that doesn't clock high but is very power efficient?

Thing is the LPE's are on the N6 process platform controller tile, which you would think would be less power efficient?

I'm all confused now.
So here is the brief on MTL/ARL the LP-E is crestmont and are on N6 in SoC without any type of cache to help them.
In LNL/PTL they are in the compute tile on N3B/18A and has special cache Called Memory Side Cache that's for LP-E so they don't starve it's a power optimized cache just to keep power low.

The Darkmont/Skymont are exactly the same cores otherwise like physically the same I have actually matched their dishots.
 
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poke01

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XPS as a sub-brand definitely has one of the best track records out there, with well built machines, well-tuned hardware and firmware and offered with enterprise-grade warranties (sometimes at no extra cost)
The last few XPS models have been questionable. Removed the headphone jack, no viable trackpad and capacitive function row and only usb-c with no other ports

They fixed most of these in the 2026 XPS but still offer only usb-C.
 

LightningZ71

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Aren't the PTL E cores made on a "fin flex" capable node now? Wouldn't it make sense to flex them to a more efficient configuration with respect to power at the expense of performance?
 
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Magio

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The last few XPS models have been questionable. Removed the headphone jack, no viable trackpad and capacitive function row and only usb-c with no other ports

They fixed most of these in the 2026 XPS but still offer only usb-C.

Don't get me wrong, I loathe the previous couple XPS iterations, the capacitive function row was on its own was just disqualifying for me. Those boneheaded decisions led me to ditching XPS to go with a Thinkpad X9. But while I disliked those models, they were still well built, well tuned and all that jazz (from what I've heard at least). In the same way, I don't dock points from all Thinkpads until the X9 for their trackpoint and odd trackpads buttons, I personally hate that but it's a debatable design choice rather than an objective flaw.

Anyway, to get back on topic the main thing about XPS is people need to stop bringing up their pricing as if it represents PTL's.
 
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Hulk

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So here is the brief on MTL/ARL the LP-E is crestmont and are on N6 in SoC without any type of cache to help them.
In LNL/PTL they are in the compute tile on N3B/18A and has special cache Called Memory Side Cache that's for LP-E so they don't starve it's a power optimized cache just to keep power low.

The Darkmont/Skymont are exactly the same cores otherwise like physically the same I have actually matched their dishots.
This is great thanks.
A couple follow up questions if you don't mind?

First, I assume the Vcore VRM telemetry is a measurement of the voltage regulator for the entire core rail and this additional power is included in the E's per core power, thus making it higher than the LPE's? That would make sense.

Second, can Intel optimize the fab cell structure of the LPE's compared to the E's fab process to tune them for lower power operation? Meaning higher threshold voltage, less leaky transistors, easier to "flip on and off" but result in less max frequency?

If this is what is going on then it is very clever. Intel has essentially built a super low power processor within the low power processor.

The LPE island is NOT simply taking some E's and lowering the frequency. It really is a self-sufficient "island of compute."
 

511

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This is great thanks.
A couple follow up questions if you don't mind?

First, I assume the Vcore VRM telemetry is a measurement of the voltage regulator for the entire core rail and this additional power is included in the E's per core power, thus making it higher than the LPE's? That would make sense.
Yes
Second, can Intel optimize the fab cell structure of the LPE's compared to the E's fab process to tune them for lower power operation? Meaning higher threshold voltage, less leaky transistors, easier to "flip on and off" but result in less max frequency?
They can but they haven't done it from the die shots I have seen for Lunar Lake it's exactly the same cores aka design someone like Tech Insight can know for sure with teardowns.
If this is what is going on then it is very clever. Intel has essentially built a super low power processor within the low power processor.

The LPE island is NOT simply taking some E's and lowering the frequency. It really is a self-sufficient "island of compute."
Well yeah it's self sufficient compute island.
 
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LightningZ71

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18A doesn't have FinFlex/NanoFlex it's a TSMC Thingy
Intel refers to their RibbonFet tech as a competing solution that supposedly allows variable ribbon configurations on the same die, thick when higher current is needed and thin when better power efficiency is needed. RibbonFet is a feature of 18a.
 

MerryCherry

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Intel refers to their RibbonFet tech as a competing solution that supposedly allows variable ribbon configurations on the same die, thick when higher current is needed and thin when better power efficiency is needed. RibbonFet is a feature of 18a.
RibbonFET is Intel's name for GAAFET, no?

TSMC styles their GAAFET transistors as Nanosheet.
 
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511

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Intel refers to their RibbonFet tech as a competing solution that supposedly allows variable ribbon configurations on the same die, thick when higher current is needed and thin when better power efficiency is needed. RibbonFet is a feature of 18a.
That's not part of 18A but 14A
 
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