Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Abwx]

LOL AMD has copied almost everything what Intel does while the opposite is not true in terms of ISA only exception being X86_64 Extension.

SSE was just Intel s version of 3DNow, albeit not as efficient as AMD s ISA, Atom kept some instructions from 3DNow wich had no equivalent within SSE.

Beside AMD was the first to implement FMA.

 

[511]

Except AMD does not down-clock on a full avx-512 implementation (Zen 5) like Intel did and does on AVX now.

Even Intel doesn't downclock on AVX-512 since Golden Cove that's a early implementation issues AMD had way more time than Intel to figure out and live off of Intel's efforts.

I wish AMD could do this with CUDA.

 

[511]

yeah this is intel's #1 issue right now. they just sold off Altera with 50% loss of investment for quick $4b cash injection. they threw TONS of money the last years trying to aggressively keep up, had to go TSMC as well

Krzanich did immeasurable damage lmao. is there like a full list of his decisions?

Dude should get an award for destroying world's Number 1 fab and design business.

 

[inquiss]

Now you know:

Intel "Nova Lake-S" CPUs to use LGA 1954 Socket, 24 x 25 mm Chipset

Based on recent shipping manifests that point to custom test hardware for its next "Nova Lake‑S" processors, Intel seems to be gearing up for a big desktop platform update. According to documents obtained by NBD.ltd, Intel isn't moving full motherboards yet. Instead, it's sending out mechanical...

www.techpowerup.com

52 cores though, and on regular desktop socket. So not comparable to Genoa/Turin which are server CPUs. So the question is what AMD has planned to counter it on regular desktop socket.

I don't think AMD does need to counter it. Will be memory starved if on two channels, and if it's a more expensive platform then it moves up a price tier to threadripper.

 

[jpiniero]

How many Cinebench Accelerators do you need tho.

 

[Fjodor2001]

I don't think AMD does need to counter it. Will be memory starved if on two channels

Not according to this.

 

[511]

How many Cinebench Accelerators do you need tho.

Cores are not for only Cinememe

 

[inquiss]

Not according to this.

Interesting data but I don't agree with the conclusion. Less memory bandwidth than a low clocked milan chip. If they give up the sorts of performance figures suggested, that's a couple of generations backwards from being memory starved.

 

[dullard]

Will be memory starved if on two channels,

Do we even know if the rumored 52-core Nova Lake will be on two channels? If DDR6 is released at the end of this year, then it is possible for Nova Lake to use it in 2026. The final DDR6 specs are to be announced this quarter. So far the DDR6 preliminary specs are for four channel memory per module, higher transfer rates (as high as DDR6-17600 in the first generation of memory chips), and lower latency.

 

[Thibsie]

SSE was just Intel s version of 3DNow, albeit not as efficient as AMD s ISA, Atom kept some instructions from 3DNow wich had no equivalent within SSE.

Beside AMD was the first to implement FMA.

You mean proper FMA4 but Intel had to do their own stupid FMA3 ? Lol Intel

 

[Thibsie]

Even Intel doesn't downclock on AVX-512 since Golden Cove that's a early implementation issues AMD had way more time than Intel to figure out and live off of Intel's efforts.

I wish AMD could do this with CUDA.

LOL who had the money and engineering ressources ? Intel. And they did crap.
This is very objective PoV.... Not !
C'mon...

 

[inquiss]

Do we even know if the rumored 52-core Nova Lake will be on two channels? If DDR6 is released at the end of this year, then it is possible for Nova Lake to use it in 2026. The final DDR6 specs are to be announced this quarter. So far the DDR6 preliminary specs are for four channel memory per module, higher transfer rates (as high as DDR6-17600 in the first generation of memory chips), and lower latency.

DDR6 is going to be server only for a while. If they do use it, which I have strong doubt over, that will prove the platform out of mainstream anyway. So it's same same vs channels.

 

[Win2012R2]

Even if you take AVX-512 for example initially when it launched it had issues and software was not ready now look at it you will find use cases for AVX-512 in almost all HPC software and few consumer software as well

Took like 10 years for AVX512 and it wasn't until Zen4 it really picked up - and AMX far far less general purpose than AVX512, plus AMD does not support it and very unlikely will, and GPUs doing better job anyway.

 

[Abwx]

You mean proper FMA4 but Intel had to do their own stupid FMA3 ? Lol Intel

AMD supported both FMA3 and FMA4 as a preventive move, i m aware that Intel tried to trick them by changing their own implementation at the last minute from FMA4 to FMA3 and believing that AMD was to use only FMA4 since Intel stated that they would use this implementation.

 

[OneEng2]

I don't think AMD does need to counter it. Will be memory starved if on two channels, and if it's a more expensive platform then it moves up a price tier to threadripper.

That was my point. It seems to get past many arguments here that there is a real world COST to high core counts and multiple memory channels (or very high bandwidth next gen memory). The user base for such a product is limited, and to attempt to put such a high cost option into the desktop/laptop would price the processor and platform clear out of the market IMO.

Do we even know if the rumored 52-core Nova Lake will be on two channels? If DDR6 is released at the end of this year, then it is possible for Nova Lake to use it in 2026. The final DDR6 specs are to be announced this quarter. So far the DDR6 preliminary specs are for four channel memory per module, higher transfer rates (as high as DDR6-17600 in the first generation of memory chips), and lower latency.

See my discussion above. How will Nova Lake compete in the general desktop and laptop markets with such an expensive platform?

 

[511]

LOL who had the money and engineering ressources ? Intel. And they did crap.
This is very objective PoV.... Not !
C'mon...

They are in serious money situation rn and are still investing in their Fab biz and design biz with APX/AVX 10.2/AMX Extensions AMD Pulled out of the Fab biz last I checked when they were in trouble.

Took like 10 years for AVX512 and it wasn't until Zen4 it really picked up - and AMX far far less general purpose than AVX512, plus AMD does not support it and very unlikely will, and GPUs doing better job anyway.

Ofc this is not true lol you will see with Zen 6 if AMD introduces AMX it will be funny 🤣.

 

[511]

That was my point. It seems to get past many arguments here that there is a real world COST to high core counts and multiple memory channels (or very high bandwidth next gen memory). The user base for such a product is limited, and to attempt to put such a high cost option into the desktop/laptop would price the processor and platform clear out of the market IMO.

See my discussion above. How will Nova Lake compete in the general desktop and laptop markets with such an expensive platform?

On mobile NVL is pin compatible with PTL (4+8+4/4+0+4 SKUs) also N2 would be slightly more expensive than Intel 18AP none of these will be $30K like the rumors at best $25K N2 doesn't have the PPA benefit proportional to price increase for 50%.

For Desktop 8+16 will also exist last I checked many tiles have back in-house for NVL including 18A iGPU only the compute tile has been leaked for N2 as of now. IO and SoC can be unified share across desktop/Mobile and will be on I3.

AMD is going to use N4C for SOC/IO and N2 for Zen 6 dies
Only if someone has any estimate for 8+16 die and Zen 6 die.

Also be ready for price increase regardless of AMD/Intel N2 is not cheap.

 

[DrMrLordX]

... and compete with AMD on price? I think not. Intel is already in a big financial pinch. They can't afford to throw money at the problem any longer IMO.

If they're actually releasing a 52c chip, they're not competing on price. Certainly not with a dual-channel premium desktop competitor.

 

[Win2012R2]

Ofc this is not true lol you will see with Zen 6 if AMD introduces AMX it will be funny

How about this - if Zen 6 introduces support for AMX then I'll delete my account on here, and if it does not - then you will delete yours, deal?

 

[Thibsie]

Of course AMD will back AMX. Zen 6 or Zen 7 who knows but they will.
It is everybody's interest, for both Intel and AMD.
Nobody wins if there are incompatibilities.

 

[Win2012R2]

Nobody wins if there are incompatibilities.

Almost nobody is using AMX, it's completely irrelevant for 99.999%. Anybody who is remotely serious about AI or just wants to play with it will use Nvidia GPUs, and if AMD does not support it (which I can't see why would they with their own GPU line) then it's totally dead, it's much strategically better for AMD to have Intel suffer penalties of using them and not implementing themselves, so of course they won't say if they will or won't support it.

Simple client (where is no AMX) every day "AI" will be done on NPU which is low power, when AMX turns on it downclocks just like original AVX512 and we know how well that worked in occasional work loads.

AMX got 8 register "tiles", with total size of 8 KiB - that's like 1024 general purpose 64 bit registers, this thing is huge.

Intel is about to fire 20% of staff, that ain't going to be all "middle-managers", they will have to cut some things proper - AMX as a complete dead end is one of the prime things to cut, especially so because it's not even in client and just increases silicon size, Intel can't afford to put big chunks of useless for most silicon in to server CPUs.

 

[NTMBK]

SSE was just Intel s version of 3DNow, albeit not as efficient as AMD s ISA, Atom kept some instructions from 3DNow wich had no equivalent within SSE.

Beside AMD was the first to implement FMA.

3DNow and SSE are totally different. 3DNow acts on the MMX registers, which are in turn aliased on the x87 registers, and only uses 64 bit vectors. It also inherited all the MMX problems of mixing with x87 code. SSE introduces completely new 128 bit vector registers separate from the x87 ones. It's a completely different (and better) instruction set.

 

[Win2012R2]

3DNow and SSE are totally different. 3DNow acts on the MMX registers, which are in turn aliased on the x87 registers, and only uses 64 bit vectors. It also inherited all the MMX problems of mixing with x87 code. SSE introduces completely new 128 bit vector registers separate from the x87 ones. It's a completely different (and better) instruction set.

Typical cheap approach from AMD, very much same attitude taken with ray tracing

 

[511]

How about this - if Zen 6 introduces support for AMX then I'll delete my account on here, and if it does not - then you will delete yours, deal?

This is a bit extreme i will stay offline for a 6 days cause it's Zen 6 🤣

 

[511]

Almost nobody is using AMX, it's completely irrelevant for 99.999%. Anybody who is remotely serious about AI or just wants to play with it will use Nvidia GPUs, and if AMD does not support it (which I can't see why would they with their own GPU line) then it's totally dead, it's much strategically better for AMD to have Intel suffer penalties of using them and not implementing themselves, so of course they won't say if they will or won't support it.

Simple client (where is no AMX) every day "AI" will be done on NPU which is low power, when AMX turns on it downclocks just like original AVX512 and we know how well that worked in occasional work loads.

AMX got 8 register "tiles", with total size of 8 KiB - that's like 1024 general purpose 64 bit registers, this thing is huge.

Intel is about to fire 20% of staff, that ain't going to be all "middle-managers", they will have to cut some things proper - AMX as a complete dead end is one of the prime things to cut, especially so because it's not even in client and just increases silicon size, Intel can't afford to put big chunks of useless for most silicon in to server CPUs.

If you can give me a proof of AMX Downclocking 🫠🫠