Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

In server loads, SMT has gained AMD 40% per pheonix reviews. For a desktop application, while 30% is certainly less than 40%, it is still considerable.

I also question the general use of Spec Int as a general performance metric. Arrow Lake really gets taken to the cleaners when the code has lots of back and fourth memory access. It really needs things to fit and STAY in the local L2. Skymont gets in trouble with lots of branches. I think this makes for a really tricky scheduler.

Yup code spilling to L3 is disaster in ARL maybe due to 84 Cycle Latency in ARL L3?

I am hoping to see SMT and AVX512 in Intel's next generation. They can't keep on having less of everything than AMD and expecting people to buy them (at least not at the same price).

Be ready for AVX 10/256 where Intel will not give you 512 Data path on client but will give the full Instructions at 256b and a bit more and no fragmentation!

Just to be fair, when AMD had dismal single threaded performance, but more cores, AMD suddenly moved the goal post to MT .... which at that time was a small amount of applications. Intel bet on high performance single core and won hearts and minds.

I see AMD doing the same thing today with Zen 5 and Zen 5 X3D. Seems like this message still works today.

Peak Gaming Performance sells i am wondering though how will 144MB L3 on Intel will do on NVL too long to wait

I am surprised more people aren't talking about how great Lunar Lake is in thin and light. Seems like that product really hit a good cord, but all anyone cares about is high performance desktop benchmarks. Strange.

There was a LNL laptop going for $650 i was like i can't buy it that was U5 with 16GB ram but it was decent you can't find a better deal

https://www.bestbuy.com/site/asus-vivobook-s-14-14-oled-laptop-copilot-pc-intel-core-ultra-5-16gb-memory-512gb-ssd-neutral-black/6595523.p?skuId=6595523&affgroup=%22Content%22

 

[DavidC1]

He is clearly confusing 285K for P core and 258V for E core, when 285K here is also E core, the difference in IPC between the two is down to using a much higher latency LPDDR and lower cache configuration in Lunar Lake, among other things.

Is it confusion?

 

[Abwx]

Is it confusion?

There s no confusion, even if we take a very optimistic 40% SMT yield in everything
the numbers talk by themselves, with 16 cores + SMT you have the equivalent of 22.4 SMT less cores of comparable IPC, with 24 cores among wich 8 have same IPC and 16 say your theorical 10% deficit since SKT is supposed to be better than Z4, you ll get 8 + 16 x 0.9 = 22.4.

So the same amount, but since 24 threads scale quite better than 32 then the 285K should beat the 9950X in about everything knowing that the 8 P cores work at higher MT frequency than the Zen 5 cores, and that the 16 SKT cores work at about the same frequency than the latter, and remember, that s with a 40% SMT yield figure that does not occur homogeneously, let alone a same scaling up to 32T compared to 24T.

 

[Meteor Late]

There s no confusion, even if we take a very optimistic 40% SMT yield in everything
the numbers talk by themselves, with 16 cores + SMT you have the equivalent of 22.4 SMT less cores of comparable IPC, with 24 cores among wich 8 have same IPC and 16 say your theorical 10% deficit since SKT is supposed to be better than Z4, you ll get 8 + 16 x 0.9 = 22.4.

So the same amount, but since 24 threads scale quite better than 32 then the 285K should beat the 9950X in about everything knowing that the 8 P cores work at higher MT frequency than the Zen 5 cores, and that the 16 SKT cores work at about the same frequency than the latter, and remember, that s with a 40% SMT yield figure that does not occur homogeneously, let alone a same scaling up to 32T compared to 24T.

So you were talking about ST IPC and now you have moved to MT?

 

[511]

There s no confusion, even if we take a very optimistic 40% SMT yield in everything
the numbers talk by themselves, with 16 cores + SMT you have the equivalent of 22.4 SMT less cores of comparable IPC, with 24 cores among wich 8 have same IPC and 16 say your theorical 10% deficit since SKT is supposed to be better than Z4, you ll get 8 + 16 x 0.9 = 22.4.

You can Spam Skymont better and keep the area in change Make it 5+24 or 4+27 🫠🫠 you can compensate logical cores for Physical core if you can cram more in the same area

 

[Abwx]

So you were talking about ST IPC and now you have moved to MT?

That s not worse than estImations that cant totaly isolate the core under test,
since you cant disable all P cores and that there will be at least one wich is active how do you measure an e core throughput with enough precision ?

Computerbase said that the usual tools to stick a process to a given core doesnt work with Intel s new gens contrary to ADL/RPL.

So what is the footprint of the P core in thoses tests when done in ST, obviously the difference between the 258V and the 285k cant come from a better cache or RAM access as we re talking ST, there cant be any bottleneck otherwise it would be a disaster in MT if in ST there s already cache and RAM access limitations.

 

[OneEng2]

There s no confusion, even if we take a very optimistic 40% SMT yield in everything
the numbers talk by themselves, with 16 cores + SMT you have the equivalent of 22.4 SMT less cores of comparable IPC, with 24 cores among wich 8 have same IPC and 16 say your theorical 10% deficit since SKT is supposed to be better than Z4, you ll get 8 + 16 x 0.9 = 22.4.

So the same amount, but since 24 threads scale quite better than 32 then the 285K should beat the 9950X in about everything knowing that the 8 P cores work at higher MT frequency than the Zen 5 cores, and that the 16 SKT cores work at about the same frequency than the latter, and remember, that s with a 40% SMT yield figure that does not occur homogeneously, let alone a same scaling up to 32T compared to 24T.

Moving the goal post here a bit?

Ok, let's talk about MT overall processor performance then.

Arrow Lake gets beat by Zen5 in nearly every MT benchmark with the exception of CB24 Where I believe bandwidth is a significant factor.

If you look at total performance, you need to also consider clock speed of all cores, not just IPC and number of cores. You also need to take into account SMT effects and the performance on real world applications.

This isn't just a math exercise.

 

[OneEng2]

And Arrow Lake enjoys a process advantage as well.

 

[511]

Arrow lakes fine tune mechanism destroys power at higher end anyway so the gains of process are negated for multi thread

 

[OneEng2]

Arrow lakes fine tune mechanism destroys power at higher end anyway so the gains of process are negated for multi thread

One could argue the the process is taken full advantage of.... But that simply means the design has some issues IMO. In this case, latency.

 

[SiliconFly]

.

 

[igor_kavinski]

I wouldn't call Lion Cove a total disaster, but it's very close to being one. Not performant enough, which brings the overall performance down.

IPC uplift over 14900KS is real but doing the disaggregated experiment with it destroyed almost all gains that could've been had.

 

[511]

View attachment 113712

IPC uplift over 14900KS is real but doing the disaggregated experiment with it destroyed almost all gains that could've been had.

Yeah the funny thing is Nova Lake will look insane with the changes in ST
One Tick Cougar Cove (8%)
One Tock Panther Cove(15%)
Roughly 25% + addition of IPC that lost due to their L3 AND NGU

 

[SiliconFly]

.

 

[igor_kavinski]

Looks like 2025 too won't be a good year for Intel.

Only if the fab expenses drag them down again. AMD never has enough supply to fulfill demand so Intel will still get decent sales no matter what product they put out.

 

[511]

intel's H2 2025 hinges on 18A tbf

 

[igor_kavinski]

https://pixinsight.com/benchmark/index.php?sort=cpu&os=all

Looks bad but maybe not that bad since the 9950X scores go as low as 30K. Decent showing for a single run.

 

[511]

https://pixinsight.com/benchmark/index.php?sort=cpu&os=all

View attachment 113717

Looks bad but maybe not that bad since the 9950X scores go as low as 30K. Decent showing for a single run.

Linux vs Windows causing the delta in 9950X

 

[SiliconFly]

.

 

[OneEng2]

Nope. RH clearly mentioned in the interview that the high latency is caused by a combination of bad scheduling + core parking. It's the wake up delay that causes the latency. There is no "latency issue" per se. Also, not all fixes are available at the moment. The full suit of fixes is coming this jan. Should solve most of these issues.

Generally speaking:
I think we're missing the bigger picture. The E cores are excellent. Very performant, very efficient & has better PPA than Zen 5C. Skymont is an amazing core. The problem lies with the P core. The damn Lion Cove.

Last gen Meteor Lake RWC was a total disaster. And this gen Lion Cove has barely shown any ST improvement (forget efficiency for a while). I wouldn't call Lion Cove a total disaster, but it's very close to being one. Not performant enough, which brings the overall performance down.

Not sure about any interview, but the bench testing I have seen for the latency clearly shows the huge deficit Arrow lake has in latency compared to Zen 5.

I think using CB single threaded benchmarks for representing general single threaded application work is misleading. CB tends to be quite bandwidth heavy, and branch light. This falls right into Arrow Lakes sweet spot IMO.

Applications that do not fit into the L2 and have lots of branches perform badly on Arrow lake due to the latency issues.

Now, I do agree, that when a new architecture comes out having fixed this latency, Lion Cove may roar quite loudly. I think Skymont is already doing about as well as its engine can.

As for the "bigger picture", Arrow Lake performs below Zen 5 in most applications and sometimes below 14XXXK IIRC. This is IMO due to the latency issue in the current design. Intel is burning through cash paying for 18A bring up and paying for premium wafers at TSMC for its processors.

I agree that 18A is a turning point for intel, but as others have stated, it will be another 2 years beyond 18A before the financial impact is resolved.

We will see if Intel can remain the "Intel" of today for that long.

 

[SiliconFly]

.

 

[OneEng2]

I sincerely hope these words come true. I'm not very sure about Panther Lake as it appears to be a bit incremental. But should solve all ARL issues and bring the platform to full potential. And most importantly, I think Nova Lake with Arctic Wolf is the one. The real game changer.

Me too.

It is my understanding that Panther Lake is a laptop part with its highest configuration -H being 4P + 8E + 4ELP (total of 16 cores). Still, this may be more potent than we think if Intel can fix the latency problems they currently have.

Nova is just so far out that it is hard to imagine investors waiting that long for a product that breaks away from the competition .... and Nova may well have to compete with Zen 6 vs Zen 5 variants today and in 2025.

 

[DZero]

Only if the fab expenses drag them down again. AMD never has enough supply to fulfill demand so Intel will still get decent sales no matter what product they put out.

The issue is that they were the only players in the Windows market, but once Qualcomm estabilishes and nVIDIA + Mediatek appears.... the situation will become wild.

 

[SiliconFly]

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[ajsdkflsdjfio]

Nope. Qualcomm's foray into the laptop segment with it's Snapdragon X Elite was not just a disaster but a total bloodbath. Considering the extremely poor sales & very high return rates, ARM can't be considered a x86 competition for the foreseeable future (excluding Apple which plays a different game altogether).

Yup, Apple is able to effectively sell ARM products because the regular Mac users were already used to the more limited program compatibility that comes with Mac, and the key programs that already worked well on x86 mac were able to be converted to work just as well on ARM due to Apple's heavy draw power.

I just don't see non-apple ARM taking market share anytime soon unless there is a large push by Microsoft to make ARM work flawlessly. The average Windows user isn't going to accept kneecapped compatibility with all the various third-party and obscure programs they like to typically use on their x86 windows machine.