Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Hulk]

I thought this data was worth reorganizing.

 

[Markfw]

I thought this data was worth reorganizing.

No 9950x ? the competition for 285k ?

 

[cannedlake240]

Not something incredible for a 2028 core. Good, but not incredible.

Given their current state matching M series will be a truly heroic achievement on the same level as Zen. Apple themselves weren't a struggling company during the last decade

 

[jdubs03]

Given their current state matching M series will be a truly heroic achievement on the same level as Zen. Apple themselves weren't a struggling company during the last decade

Pigs will fly before this happens. So indeed, it would have to be Herculean.

 

[DavidC1]

Given their current state matching M series will be a truly heroic achievement on the same level as Zen. Apple themselves weren't a struggling company during the last decade

If they can't match it then the conclusion is that the enormous gap is due to the ISA, which I flat out don't buy. Heard of too many excuses in both directions.

It was back in the Athlon 64 days when some outlets(really good ones at that) express doubts whether perf/clock could improve. It did, and today's CPUs far surpass that chip. The E cores ground A64 to the dust.

I do believe it is the capable people leaving that made Apple Mx only get little gains. You have Jim Keller at Tensorrent focusing on AI now. You have intellers saying that they pulled engineers off the Royal Core team to work on GPUs and AI. Tell me that doesn't have a negative impact on CPU teams?

All the way to Skymont they managed to get linear scaling between core area increase and scalar integer performance. And suddenly it'll barely scale from there? How does that logic even work when the Skymont E core is one of the smallest modern cores?* It has way more room to grow, even in an efficient way, and then add to growing to a 2.xmm2 core on TOP of that.

@Hulk Add 5% to both Lion Cove and Skymont with a good fabric.

*Think of how a "9-issue" Skymont with 26 dispatch ports is only 27% larger than Oryon-M with 4-issue and 8 ports. Either the E core team is really, really good at dense chips despite being on x86(questionable), or they still had to make compromises.

 

[cannedlake240]

they can't match it then the conclusion is that the enormous gap is due to the ISA, which I flat out don't buy. Heard of too many excuses in both directions.

Nah it just means Apple has the engineering prowess and finances to support that. They can probably afford multiple projects like Royal core working in parallel on all sorts of innovations. In contrast even back when Intel had 95% market share pretty sure they weren't known for high pay

You have intellers saying that they pulled engineers off the Royal Core team to work on GPUs and AI

That just seems like hopium, in reality they all probably left for the new startup founded by the same team leaders that allegedly set out to implement their vision on Risc V, or other companies where grass is greener. The program apparently wasn't frozen it was completely abandoned

All the way to Skymont they managed to get linear scaling between core area increase and scalar integer performance.

Well if they exhausted all the low hanging fruit then yeah improvements are likely to slow down

 

[511]

The Royal Core program was abandoned but not their Ideas and things they have already worked out

 

[DavidC1]

Well if they exhausted all the low hanging fruit then yeah improvements are likely to slow down

Yea, no this is nonsense, sorry.

They can catch up to Lion Cove by making up the area just by adding more caches. Just watch, they'll be able to claim equal performance to previous generation P cores, not just per clock performance, all with 1.5mm2 core on Arctic Wolf.

That just seems like hopium, in reality they all probably left for the new startup founded by the same team leaders that allegedly set out to implement their vision on Risc V, or other companies where grass is greener. The program apparently wasn't frozen it was completely abandoned

Intel had to abandon the project, because the important numbers left, enough that they could create a startup. And it started because they pulled members off the project to focus on "AI".

Another team to watch is Qualcomm's Nuvia team. The second gen is quite an improvement.

Nah it just means Apple has the engineering prowess and finances to support that. They can probably afford multiple projects like Royal core working in parallel on all sorts of innovations. In contrast even back when Intel had 95% market share pretty sure they weren't known for high pay

Nothing to do with pay. Intel management simply told after Sandy Bridge that "we don't need to focus on uarch". Hence the stagnation.

 

[511]

Biggest idocity don't focus on core buisness and let us get ourselves into problems
They had the moat of TSMC+Nvidia combined and they killed it

 

[Abwx]

I thought this data was worth reorganizing.

Those numbers are truncated, here s Huang s numbers, the score for the 265K is comparable to those scores for the 285K, as well as for the 14900K, but seems that Raichu is completely wrong for Zen 5, indeed in all INT apps that are lowly threaded Zen 5 is faster than ARL.

 

[cannedlake240]

Nothing to do with pay.

Idk ex-/intellers complaining about uncompetitive pay at intel goes back when they were still counted one of the "big tech" companies. Now they can't even afford it and are constantly slashing bonuses etc. How can this and culture problems not be a problem for retaining talent?

Yea, no this is nonsense, sorry.

Never said Atom will just stop improving. Just that uplifts may not continue at the same pace

And it started because they pulled members off the project to focus on "AI"

Exist50 on reddit has since said that they all pretty much left the company...

 

[FlameTail]

Idk ex-/intellers complaining about uncompetitive pay at intel goes back when they were still counted one of the "big tech" companies. Now they can't even afford it and are constantly slashing bonuses etc.

That does not surprise me.

Intel has 2x the revenue of AMD, but 4x the employee count.
Intel has 50% more revenue than Qualcomm, but 2x the employee count.
The disparity is even bigger with Nvidia.

 

[511]

Those numbers are truncated, here s Huang s numbers, the score for the 265K is comparable to those scores for the 285K, as well as for the 14900K, but seems that Raichu is completely wrong for Zen 5, indeed in all INT apps that are lowly threaded Zen 5 is faster than ARL.

Diffrent compilers and flags used 🙂

 

[511]

Middle Management should have been layed off in this wave just wipe One tier

 

[Hulk]

Those numbers are truncated, here s Huang s numbers, the score for the 265K is comparable to those scores for the 285K, as well as for the 14900K, but seems that Raichu is completely wrong for Zen 5, indeed in all INT apps that are lowly threaded Zen 5 is faster than ARL.

What do you mean by truncated? He left digits off the result?

Or do you mean all of Raichu's results are just wrong?

 

[Abwx]

What do you mean by truncated? He left digits off the result?

Or do you mean all of Raichu's results are just wrong?

He states 10.46 in Spec_int for the 9700X while Huang has 12.6 for the 9950X, at isofrequency that s a 16% difference, notice that Huang has the same numbers for ARL and RPL as Raichu.

 

[Hulk]

He states 10.46 in Spec_int for the 9700X while Huang has 12.6 for the 9950X, at isofrequency that s a 16% difference, notice that Huang has the same numbers for ARL and RPL as Raichu.

I believe the numbers you are quoting for Raichu are at stock clocks, which would make sense, because the 9950X clocks higher than the 9700X right?

Someone here said that the Raichu results where only core names are listed are iso-frequency. The ones where CPU names are listed are stock frequency. We don't know the frequency either were run at though.

 

[Abwx]

I believe the numbers you are quoting for Raichu are at stock clocks, which would make sense, because the 9950X clocks higher than the 9700X right?

Someone here said that the Raichu results where only core names are listed are iso-frequency. The ones where CPU names are listed are stock frequency. We don't know the frequency either were run at though.

9950X clocks merely 4% higher with a good chip than an average 9700X, at 5.7GHz it would score only 10.84 according to Raichu s 10.46 number wich is at 5.5GHz, that s quite a stretch from Huang s 12.6 for the 9950X.

The fact that his ARL/RPL s numbers are about the same as Huang is an indication that he did the tests at stock frequencies for all CPUs, as for Huang he has Zen 5 perf/GHz at 2.21 while it s 2.02 for ARL.

 

[511]

It's all in the compiler flags 🙂
I have found the gain from Intel 3-> 20A(10% ppw) and 20A -> 18A (10% ppw)
From official Intel sources when they were developing it

So the gain target was about 20% and they ended with 15%

 

[Hulk]

9950X clocks merely 4% higher with a good chip than an average 9700X, at 5.7GHz it would score only 10.84 according to Raichu s 10.46 number wich is at 5.5GHz, that s quite a stretch from Huang s 12.6 for the 9950X.

The fact that his ARL/RPL s numbers are about the same as Huang is an indication that he did the tests at stock frequencies for all CPUs, as for Huang he has Zen 5 perf/GHz at 2.21 while it s 2.02 for ARL.

I don't know how I got in the position to be defending Raichu's results. I thought I was doing a favor to the forum by making them easier to read.

If the forum assessment is they are unreliable garbage I will delete the table from my post.

I agree with you BTW. One of the two tests, either Raichu's or Huang's, is bugged.

This is why I always say we can't trust any results that were run by someone on this forum so we can get all of the testing procedures in detail. Ask questions, get replies.

 

[Hitman928]

It's all in the compiler flags 🙂
I have found the gain from Intel 3-> 20A(10% ppw) and 20A -> 18A (10% ppw)
From official Intel sources when they were developing it

So the gain target was about 20% and they ended with 15%

Originally, Intel 3 to 20a was supposed to be a 15% improvement in ppw.

 

[511]

Originally, Intel 3 to 20a was supposed to be a 15% improvement in ppw.

I have seen slides with 10-15% estimate as well but looking at everything they played marketing tricks by saying " upto 15% " apparently they were not sure either what they will get

 

[Hitman928]

I have seen slides with 10-15% estimate as well but looking at everything they played marketing tricks by saying " upto 15% " apparently they were not sure either what they will get

These quotes are always up to. Either way, it started at 15% + 10% and is now 15%.

Edit: she was also talking about saying it was 10% when they first announced it, which is wrong, everyone reported it was 15% at the time. So, either she’s trying to revise history to make it seem like they weren’t going to miss their target (and 20a ended up cancelled anyway) or she doesn’t remember what they told the world back at the time of announcement.

 

[511]

These quotes are always up to. Either way, it started at 15% + 10% and is now 15%.

At least we know the real goals with Ann Kehller i would take that better than Marketing Slides

 

[OneEng2]

If they can't match it then the conclusion is that the enormous gap is due to the ISA, which I flat out don't buy. Heard of too many excuses in both directions.

It was back in the Athlon 64 days when some outlets(really good ones at that) express doubts whether perf/clock could improve. It did, and today's CPUs far surpass that chip. The E cores ground A64 to the dust.

I do believe it is the capable people leaving that made Apple Mx only get little gains. You have Jim Keller at Tensorrent focusing on AI now. You have intellers saying that they pulled engineers off the Royal Core team to work on GPUs and AI. Tell me that doesn't have a negative impact on CPU teams?

All the way to Skymont they managed to get linear scaling between core area increase and scalar integer performance. And suddenly it'll barely scale from there? How does that logic even work when the Skymont E core is one of the smallest modern cores?* It has way more room to grow, even in an efficient way, and then add to growing to a 2.xmm2 core on TOP of that.

@Hulk Add 5% to both Lion Cove and Skymont with a good fabric.

*Think of how a "9-issue" Skymont with 26 dispatch ports is only 27% larger than Oryon-M with 4-issue and 8 ports. Either the E core team is really, really good at dense chips despite being on x86(questionable), or they still had to make compromises.

Sure, performance per clock has continued to increase over time; however, I would argue that it does so by using more transistors to do it.

More decodes, more dispatches, more execution units, bigger cache, more set associativity, more complex branch prediction units, etc, etc, etc.

Sometimes new instruction sets and data paths are introduced which improve performance per clock, but again, at a penalty of more transistors.

My question is, have we had any innovations that with the SAME transistor count, performance per clock is improved dramatically?

I think this type of argument is precisely why SMT is such a design win. For very little additional transistors, you can get 40% more performance per clock from the design.

As we move into the period of history where Moore's law is truly dead (or severely limited), I think it will come down to how well you run your business, including how well you taylor your products to meet different market demands. Intel has (for decades) enjoyed a process advantage lead over everyone else. I think that this gravy train just dried up though, and now Intel has to find a business model that is competitive.

Intel needs to (very quickly) decide if it is a foundry or a design house. Right now, they seem to believe they can continue to be both. I don't see the math though.

As far as the excellence of Skymont, I suspect it isn't as rosy as it appears for all workloads. We need some detailed analysis on what Lion Cove is doing vs what Skymont is doing in Arrow Lake.