Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[jdubs03]

Its on a better node so thats kind of given to be smaller. The performance improvements are pretty mundane as well.

Fair appraisal. That surely helps. But still if we’re just looking at core size and comparing to the M4, Oryon-L does look pretty good performance wise while being considerably smaller.

 

[FlameTail]

wait, are these just the cores themselves. No L2?

If so how can 10-wide core with a 960 ROB be smaller than Lion cove and Zen5C.

@Kepler_L2 , whats going on here?

EDIT: Well it is on N3E

The source says private L2 caches are included into area.

M4-P : 3 mm² N3E
Lion Cove : 4.5 mm² N3B
Zen 5 : 4.15 mm² N4P

Lion Cove has a 2.5 MB private L2 cache. But I am pretty sure that even if we subtract the L2 area, Lion Cove will be bigger than M4 P-core. Speaks a lot about how bloated Intel's Cove designs are. (And Lion Cove is even on the slightly denser N3B node!)

 

[GTracing]

View attachment 110829
Source

This includes the L2 cache for Intel and AMD cores, but not for Qualcomm or Apple cores. The rationale is that the L2 on the X86 CPUs is private, but it's still a dubious way of measuring the core in my opinion.

Plus they aren't even consistent because they include the L2 for skymont even though it's shared.

 

[cannedlake240]

The source says private L2 caches are included into area.

M4-P : 3 mm² N3E
Lion Cove : 4.5 mm² N3B
Zen 5 : 4.15 mm² N4P

Lion Cove has a 2.5 MB private L2 cache. But I am pretty sure that even if we subtract the L2 area, Lion Cove will be bigger than M4 P-core. Speaks a lot about how bloated Intel's Cove designs are. (And Lion Cove is even on the slightly denser N3B node!)

LNC large area probably has to do with higher clocks as well. It's 5.7Ghz vs 4.5 on M4

 

[FlameTail]

Fun Fact: Lunar Lake has more cache than M4

	M4	LNL
CPU	4P 4E	4P 4LPE
L0d	N/A N/A	48 KB × 4 N/A
L1d	128 KB × 4 64 KB × 4	192 KB × 4 32 KB × 4
L1i	192 KB × 4 128 KB × 4	64 KB × 4 64 KB × 4
L2	16 MB shared 4 MB shared	2.5 MB × 4 4 MB shared
L3	N/A	12 MB shared
SLC	8 MB	8 MB
Total	30 MB	35.6 MB

 

[adroc_thurston]

Fun Fact: Lunar Lake has more cache than M4

Kinda flawed metric since Apple stashes like a kiloton of SRAM in the display core.

 

[Kepler_L2]

wait, are these just the cores themselves. No L2?

If so how can 10-wide core with a 960 ROB be smaller than Lion cove and Zen5C.

@Kepler_L2 , whats going on here?

EDIT: Well it is on N3E

No SMT and 128-bit vectors.

 

[adroc_thurston]

If so how can 10-wide core with a 960 ROB be smaller than Lion cove and Zen5C.

Paltry SIMD and lower clock targets.
SKT is a better comparison point since it also targets mid 4s as the upper shipped clk bin.

 

[FlameTail]

SoC area comparison (Measurements my own).



Notes
- Lunar Lake and M4 are on 3nm, whereas X Elite and Strix Point are on 4nm. So areas are not directly comparable between them.
- All numbers are in mm²
- Cores area with asterisks (*) include the private L2 cache
- Lunar Lake SoC area is the N3B Compute Tile
- Apple M4 NPU area is suspiciously small, but I have double checked with their iPhone SoCs, and they also have ~5 mm² NPUs

Sources
- Lunar Lake and Strix Point die shot annotations by Nemez
- M4 die shot annotation by Frederic Orange
- X Elite dieshot annotation by Piglin

 

[branch_suggestion]

Can somebody measure CPU cluster sizes already?

 

[poke01]

pple M4 NPU area is suspiciously small, but I have double checked with their iPhone SoCs, and they also have ~5 mm² NPUs

It probably doesn't support all formats

 

[poke01]

No SMT and 128-bit vectors.

Paltry SIMD and lower clock targets.
SKT is a better comparison point since it also targets mid 4s as the upper shipped clk bin.

True. That makes AMD's core super impressive and its on N4P. Zen6 on N3E/P is gonna be great to look forward too.

 

[adroc_thurston]

That makes AMD's core super impressive and its on N4P

Yeah, for all the Zen5% memes, PPA is still pretty solid on these even accounting for the bulkiest SIMD implementation among the modern CPU cores.

Now if only someone slaughetered a poor poor Turin-D ES to find out Z5c@N3e area.

 

[poke01]

Yeah, for all the Zen5% memes, PPA is still pretty solid on these even accounting for the bulkiest SIMD implementation among the modern CPU cores.

I find all the modern cores to be good expect lion cove. Like what does it excel at?

 

[adroc_thurston]

Like what does it excel at?

Being Really Bad. (no, seriously).

 

[cannedlake240]

I find all the modern cores to be good expect lion cove. Like what does it excel at?

Cb 2024 1T score? Also the first x86 core with traditional 8 wide decode

 

[adroc_thurston]

Cb 2024 1T score?

Apple just rolls it over.

Also the first x86 core with traditional 8 wide decode

Special olympics.

 

[511]

Nothing outside of AMX

 

[dttprofessor]

Intel reject to put more cash on P core, let's waiting for E core.

 

[Thunder 57]

Cb 2024 1T score? Also the first x86 core with traditional 8 wide decode

I'd love to see how much that 8 wide decode helps. AMD's 2x4 decode seems to be very much throughput first and I think that is why it disappointed many in gaming. I wonder how a mythical 6 wide decode would've done. Probably more balanced between client/server, but we know where the money is.

Maybe C&C will have an article on Lion Cove about it, if there isn't already.

 

[Joe NYC]

View attachment 110829
Source

Lion Cove is a big problem for Intel, in how bloated it is.

After density improvement of N3 over N4 (up to 40% in logic), after removal of HT, after removal of AVX-512, it is still bigger than Zen 5 core.

 

[Joe NYC]

Intel reject to put more cash on P core, let's waiting for E core.

It may not be a question of money. It is more likely the team in charge of the P-Cores that is lost and lacking vision how to advance.

 

[DavidC1]

Now if only someone slaughetered a poor poor Turin-D ES to find out Z5c@N3e area.

You don't need to. We know SP6 sizes and AMD has a Turin-D shot.

I measured 1.9mm2 for 5c 3nm without L2 cache. It's only slightly smaller than N4. Likely 512-bit FP is the difference.

@poke01

It would be so hard for ARM even with Apple cores to be good at gaming. There is so much optimisation that goes into x86 in terms of software for games.

I'm talking about a theoretical x86 core that has M4 level performance.

 

[adroc_thurston]

You don't need to. We know SP6 sizes and AMD has a Turin-D shot.

Yeah but the CCD has a really weird(tm) aspect ratio, making any non-dieshot measurements poo.

 

[DavidC1]

Yeah but the CCD has a really weird(tm) aspect ratio, making any non-dieshot measurements poo.

https://www.amd.com/content/dam/amd/en/images/products/data-centers/2909511-amd-zen5c-chip.png

Seems pretty good to measure with to me.

Cb 2024 1T score? Also the first x86 core with traditional 8 wide decode.

So the P core team spent too much resources and time on something that didn't bring them lot of performance. No balance in design. I bet they could have kept it 6-wide and got the same performance. Could have ended up 5-10% smaller in core and improve TTM.