Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[AcrosTinus]

This too? https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41321702

More on the numbers:
if these are indeed true and there were no driver issues, Intel is cooked. What am I seeing my eyes......

 

[AcrosTinus]

Here's hoping you don't have to distrust all the reviews tomorrow.

I never distrust a consensus.
The issue is only to know how far Intel has fallen, I expected a dip from Raptor not Rocket Lake performance....

 

[igor_kavinski]

More on the numbers:
if these are indeed true and there were no driver issues, Intel is cooked. What am I seeing my eyes......

Wonder how many Intel employees have their parachutes at the ready...

 

[AcrosTinus]

Wonder how many Intel employees have their parachutes at the ready...

I won't blame them, their tiles seem to be quite bad, higher latency than AMDs cheaper approach somehow....

No wonder they started reducing the complexity on the server parts, xeon 6 is in fact 3 monolithic dies and turin is really a chiplet design because the smallest part is a 8 core cluster not a 44 core one.

 

[adroc_thurston]

Wow ARL-S is a lot worse in vidya than I expected. 3M L2 didn't help one bit I guess.

Wonder how many Intel employees have their parachutes at the ready...

Intel already gave out a ton of chutes in voluntary early separation programs.

 

[511]

I won't blame them, their tiles seem to be quite bad, higher latency than AMDs cheaper approach somehow....

No wonder they started reducing the complexity on the server parts, xeon 6 is in fact 3 monolithic dies and turin is really a chiplet design because the smallest part is a 8 core cluster not a 44 core one.

EMIB and Foveros are two different things it's not the tiles but the fabric the Ring and NOC dragging it down

 

[desrever]

So Zen 4 gaming performance was too optimistic, it seems ARL is competitive with Zen 3.

 

[igor_kavinski]

it seems ARL is competitive with Zen 3.

ARL will soon have Zen 3 prices too!

 

[DAPUNISHER]

View attachment 110081

 

[igor_kavinski]

Factorio stresses all parts of memory subsystem, so there are clearly major problems there.

Crap. There go my dreams of breaking Rapydmark High 110 sec barrier for Intel CPUs

 

[511]

https://www.reddit.com/r/hardware/s/EnatrToDu5

Tiles from an Actual Intel Engineer

I can answer some of that actually. ARL is an MTL successor and ARL-S belongs to the same family of chips as MTL-S. They share a lot of DNA, right down to how tiles were laid out.

The splitting of the CPU, SoC, I/O, and GPU was done on MTL to power down parts that don't need it. You also get to pick and choose process nodes at will to balance performance and cost for each subsystem. The tiny iGPU doesn't need the absolute best, so it gets 5nm. We're not exactly making some super APU here, just drive a couple monitors. The CPU needs to be on the bleeding edge, so it gets 3nm. SoC and I/O don't generally scale down that well, so they get even older nodes than the iGPU because there's not much point in using anything better.

LNL needs everything to be super localized as they can't afford interconnect losses in that power segment as MTL-U proves, so it gets to be basically monolithic with the APU tile and I/O tile split. The die is also small enough that the yields and cost of 3nm are still very reasonable. LNL's APU tile is similar in size to some upcoming Smartphone SoCs.

Building ARL like LNL would have been insanely expensive as that's a ton of 3nm silicon, so it got carved up. I suspect the reason for the GPU being split off is to reuse MTL stuff. Even if it isn't the exact same tile, they've done a 4 Xe core iGPU on its own tile before.

IMO, and I say this as a die packaging engineer, there should be 3 tiles (plus interposer) here. The CPU cores and memory controller can go together to give the latency-sensitive cores the fastest access possible. Foveros latency isn't completely atrocious, but it's never beating being on-die. Nothing on SoC needs super low latency so that's fine, and we can combine in the GPU here so it still gets a link to the tile that has the memory controller on it rather than needing to go through the SoC tile to the CPU tile for it. I/O can stay split off by itself. Nothing on the I/O tile scales down very well, nor is there any substantial benefit to combining it with other tiles, so it can stay as is.

 

[CouncilorIrissa]

You shouldn't pay too much attention to this review, there are way too many very questionable numbers, like 14900K being 70% faster than 14900KS in Factorio update time benchmark

 

[adroc_thurston]

Factorio isn't representative of most games

It's a specific case of cache (small factory) and memory (chunggus khan one) gore.
Pretty indicative of the weak spot.

 

[511]

Basically Admitting the design was wrong and CPU+IMC should have been in the same tile

 

[511]

IMO, and I say this as a die packaging engineer, there should be 3 tiles (plus interposer) here. The CPU cores and memory controller can go together to give the latency-sensitive cores the fastest access possible. Foveros latency isn't completely atrocious, but it's never beating being on-die. Nothing on SoC needs super low latency so that's fine, and we can combine in the GPU here so it still gets a link to the tile that has the memory controller on it rather than needing to go through the SoC tile to the CPU tile for it. I/O can stay split off by itself. Nothing on the I/O tile scales down very well, nor is there any substantial benefit to combining it with other tiles, so it can stay as is.

Basically the design choices were wrong for desktop
Can someone delete this post as it is a duplicate post
Some Moderator 🙂

 

[adroc_thurston]

The CPU cores and memory controller can go together to give the latency-sensitive cores the fastest access possible

You're not gonna believe what PTL is doing

 

[SiliconFly]

.

 

[511]

You're not gonna believe what PTL is doing

I know what it is doing CPU+NPU+Video Engine+Imc 18A On same die GPU on N3E/I3 and N6 IO

 

[inquiss]

You're not gonna believe what PTL is doing

It's either doing that exact thing or completely the opposite I'm guessing from your post

 

[adroc_thurston]

It's either doing that exact thing or completely the opposite I'm guessing from your post

Compute and SOC tiles gattai into one in PTL. Only the iGP and HSIO are separate.

 

[Hitman928]

View attachment 110110

If other reviewers show what the leaked review does (more or less) and it wasn't due to a bad motherboard or something, I am curious to see if outlets will publish multiple videos on how Intel was lying about performance in their pre-release marketing slides

 

[desrever]

If other reviewers show what the leaked review does (more or less) and it wasn't due to a bad motherboard or something, I am curious to see if outlets will publish multiple videos on how Intel was lying about performance in their pre-release marketing slides

They will instead make videos on "we decided not to do gaming benchmarks", "the performance per dollar in cinebench r24 is unmatched" and "Give Intel a chance to release new bios, we need competition"

 

[poke01]

"Waste of sand" GN video incoming.

So my old 12400 is better in Factorio than a 285K. Guys I have a the best cheap Intel flagship already in my closet.

 

[gdansk]

So my old 12400 is better in Factorio than a 285K. Guys I have a the best cheap Intel flagship already in my closet.

I don't know. Results are not very typical. I will wait for other tests. I expect it to do much better if the scheduler wakes up.

 

[igor_kavinski]

I don't know. Results are not very typical. I will wait for other tests. I expect it to do much better if the scheduler wakes up.

It was someone on this forum who not sure if he was joking or serious but I think I read that Microsoft has a special Win11 patch slated for release soon after Arrow Lake.