Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[coercitiv]

Correct me if I'm wrong, or is Netburst being a failure more hindsight is 20/20? This is years before I started following hardware, but I heard that when Netburst design first started, many believed clock speeds would just keep increasing, so focusing on clockspeed at the expense of IPC sounded like a good idea initially at the time the development started. Only later on was it discovered to be a terrible idea. Going from 2Ghz to 4Ghz is 2x performance, without any change to IPC. Intel was predicting publicly that they'd be hitting 10Ghz in a few generations.

IMHO the problem everyone has with Netburst is how much it took between launching the first products and ending the madness. Taking a quick look at Wikipedia, Netburst lasted for 6 years. Since we're talking about hindsight and judging the decisions of the 2000 era through the lens of 2024, consider a modern company launching a flawed architecture today and then pursuing the goals of that arch for another 4-5 years or so.

But personally after Willamette I think they should have realized some problems but they doubled down with Prescott.

Yup, taking the path was not the problem. Pushing on in spite of all the warning signs was.

 

[vanplayer]

Does Blender CPU take advantage of AVX-512?

AFAIK rendering engines don't utilize any vector instruction set which are beyond 256bit due to technical reason, either it doesn't have any benefit or simply cannot implement. More cores/threads makes much more sense in this area. I believe Blender can utilize up to AVX2 256bit inst, nothing more than that, and Blender results database doesn't have any indication that AVX512 make sense.

 

[yuri69]

For me the astounding fact about Netburst is that so many super smart people can get lost in an area they know so well, and have lived in and studied most of their lives, yet they still end up taking a devistatingly wrong turn on a super highway with no exit for 50 miles, which made them late for an exceedingly important event.

It was simply the zeitgeist. Processors clocked faster, Netburst aimed to accelerate that trend.

AMD was apparently seriously worried about Netburst. It was so much they pursued their own Netburst - called K9. That was just after they finalized K8 (Athlon 64) and thought they couldn't compete with future Intels. But yeah, K9 was canned when it was apparent those designs would burn like 100+W with a just single core but the world was moving towards multi-cores.

As always, you can't easily simply resteer the core roadmap - it takes years to build a CPU.

 

[DavidC1]

Only later on was it discovered to be a terrible idea. Going from 2Ghz to 4Ghz is 2x performance, without any change to IPC. Intel was predicting publicly that they'd be hitting 10Ghz in a few generations.

The problem with Netburst was that the clock increase came at a significant sacrifice to performance/clock. The 1.5GHz was anywhere from 1GHz P3 to a 1.5GHz P3.

And they did it again with Prescott. Well, actually Prescott lost a lot less, but at 3.4GHz it was already using 125W, which was huge in those days. There were reports that they were expecting Prescott to reach 5.2GHz, and 5.6GHz, and 6+GHz very soon, like every 1-2 quarters.

Moore's Law and tech advancements always favor the low, meaning lower clocked, lower power, and lower cost. So as time passes, the difference between them gets reduced.

If it was 10 years ago, Apple cores may not have been so close to Intel's top chips today.

AMD was apparently seriously worried about Netburst. It was so much they pursued their own Netburst - called K9.

Very interesting. They did get Bulldozer out though.

Additionally, the power density becomes a major issue a7s you continue to scale to smaller and smaller geometries.

Power Density is pretty much the dominant factor at certain frequencies.

Overclocking World records prove this.

If they ever get microfluidic channels(which has immense hurdles to go through to make it reliable and low cost) through the die, maybe we'll get to see 7GHz chips. But what's the point really? Power efficiency is needed anyway.

 

[Det0x]

More 285k results showing up in the geekbench 6 database
Seems like average results are going down with a larger sample size, just as expected

Geekbench Search - Geekbench

btw, does anyone know where our swagger guy have gone ? Have been pretty much radio silence for a few of this thread regulars, after these latest leaks it seems (?)
+20% ST performance over the 14900KS was always fanfiction, but this seems below even my expectations, althought i did get some of my predictions right, even if i took some flak for that at the time

So we get 253w instead of 353w ?
View attachment 104699

Taken from here:

Intel says Raptor Lake microcode update will not affect overclocking and performance, new Arrow Lake/Battlemage updates - VideoCardz.com

Intel makes several claims at ASUS event in China Updates for Raptor Lake, Arrow Lake and Battlemage. Source: 小敌鸽/Weibo “小敌鸽” aka Little Pigeon is a Chinese tech blogger who has shared some first-hand information in the past. This person was invited to Intel x ASUS event (said to be an internal...

videocardz.com

 

[DavidC1]

Yup, taking the path was not the problem. Pushing on in spite of all the warning signs was.

Don't forget Tejas, which was rumored to push it even further, like 50 stages or so?

Prescott's 31 stages is with the Trace Cache hit. Without it some people said it was 38-39 stages.

 

[yuri69]

Very interesting. They did get Bulldozer out though.

Bulldozer was being prepared as the "future experimental" core - called K10 - around the time K9 was still alive.

 

[NostaSeronx]

Bulldozer was being prepared as the "future experimental" core - called K10 - around the time K9 was still alive.

Original Bulldozer was the multi-core/high IPC variant of Bobcat.
K10(AG/MB) was the simpler design to port, so original Bulldozer(JK/CM) was killed off. AMD had issues with Bulldozer's synthesised macros but not with K10's custom macros.

K9 had a single monolithic 4 ALU-PRF group w/ 4-wide decode. While K10 split the ALU-PRF in half doing 2x2 w/ 4-wide decode, shown in the MA patents for K9 and K10. However, when it went to MB the design was revised to what it launched with. The MB design was specifically changed to get into a Microsoft device that was never named. So, if anyone is wondering why it doesn't do PH's Bulldozer 2007(High IPC/16-core) or FW's K10 2002(9 GHz/quad-core) it is because of Microsoft.

"For the mobile market we are optimizing for low power, lower-cost devices; we’re focusing on power efficient devices in the desktop space, and on scalable, power efficient, highly available designs in the server space." -- "...The mobile microarchitecture could be pushed up to the desktop..." -- the main reason why DM was kicked out.
Timeline CM joins 2004, PH gains position in 2005 ==> 2007+ CM gets promoted to irrelevant position, PH leaves, etc. Why it went from K10 (2002-2004) -> Bulldozer (2005- early2007) -> Modified K10 (stole Bulldozer name, late2007-to launch).

 

[coercitiv]

btw, does anyone know where our swagger guy have gone ?

swaggers come and go, on all sides of the isle. heh, we might as well coin this term for them.

 

[Markfw]

swaggers come and go, on all sides of the isle. heh, we might as well coin this term for them.

I like that comment.
I like that I was going to say he is a (forbidden) and if his favorite company is not doing as well as predicted he will not comment.

 

[tsamolotoff]

Lotsa eggs on the faces of people who tried to play semicon Nostradamus this year

 

[majord]

Yeah, more than just one person MIA after lots of silly predictions

 

[Nothingness]

AFAIK rendering engines don't utilize any vector instruction set which are beyond 256bit due to technical reason, either it doesn't have any benefit or simply cannot implement. More cores/threads makes much more sense in this area. I believe Blender can utilize up to AVX2 256bit inst, nothing more than that, and Blender results database doesn't have any indication that AVX512 make sense.

I don't know about Blender, but some other renderers certainly benefit from AVX-512: https://www.phoronix.com/review/amd-zen5-avx-512-9950x/3

 

[Josh128]

Lotsa eggs on the faces of people who tried to play semicon Nostradamus this year

Indeed.

 

[poke01]

Until Intel has an answer for X3D I don’t see them competing with AMD for the gaming crown anytime soon.

 

[FlameTail]

Until Intel has an answer for X3D I don’t see them competing with AMD for the gaming crown anytime soon.

Doesn't AMD benefit more from X3D because their memory controller is worse? Intel will have much less to gain from putting X3D to their CPUs.

 

[poke01]

Doesn't AMD benefit more from X3D because their memory controller is worse? Intel will have much less to gain from putting X3D to their CPUs.

From a consumer standpoint, you can buy 6,000MT/s RAM and still get great performance on a X3D CPU.

What you said was true for Raptor Lake but Arrow Lake is a regression in every way for gaming, only efficiency is improved.

 

[coercitiv]

Intel will have much less to gain from putting X3D to their CPUs.

Yeah, they would only win the performance crown, big deal!

 

[511]

We need 128/256 MB eDRAM with DDR6 with RPL should be good enough 🤔

 

[Hulk]

Lotsa eggs on the faces of people who tried to play semicon Nostradamus this year

Yes, I was waaaaay off base with Skymont. I would never have guessed the IPC gain vs Gracemont would have been possible in one generation. Lion Cove is on the lower side of what I was thinking.

 

[511]

Yes, I was waaaaay off base with Skymont. I would never have guessed the IPC gain vs Gracemont would have been possible in one generation. Lion Cove is on the lower side of what I was thinking.

I will reserve my final judgement on Lion Cove until i get a Power Performance curve vs Zen 5 but Area is already Worse for P cores and on a more advanced node if Power and Performance is similar than it is bad

Skymont is hilariously Good in PPA it's just not good for Peak ST Performance that is only good in desktops

 

[tsamolotoff]

Doesn't AMD benefit more from X3D because their memory controller is worse? Intel will have much less to gain from putting X3D to their CPUs.

I'd say most of the extra performance of 13/14th gen over 12th gen was due to extra cache added and not memory performance. Also, you can't really compare intel and amd RAM controller 'quality' as they work in completely different modes - AMD can work both in gear1 and gear2 mode with DDR5, while Intel only does G2 or G4 even with Arrow Lake, Intel's controller is (or rather was) integrated into the ring bus while AMD one is connected via an interface that has inherent tradeoffs to allow it to scale better with more core clusters. Also, if your software is coded in a numa-aware fashion, you'd be able to utilize the bandwidth in a proper fashion in 1:2 mode with Zen4/5, contrary to the stigma of "amd ddr5 bad"

 

[Det0x]

Doesn't AMD benefit more from X3D because their memory controller is worse? Intel will have much less to gain from putting X3D to their CPUs.

AMD currently have the strongest/best memory controller on the X86 market with the 8000 APU series
But as with regular 7000 and 9000 series, the infinity fabric is the main bottlenect, but that's a seperated thing from the memory controller itself..

Here is one example of said IMC -> dualchannel 9800MT/s without any cudimm in normal ambient temps

 

[511]

AMD currently have the strongest/best memory controller on the X86 market wuth the 8000 APU series
But as with regular 7000 and 9000 series, the infinity fabric is the main bottlenect, but that's a seperated thing from the memory controller itself..

Here is one example stable dualchannel 9800MT/s without any cudimm
View attachment 109573

I think LNL has the best one 🙂

 

[poke01]

What will be peak score of 285K in CB24 ST
I think around 150-152.