Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

do you have proof of this happening in the last 4 years? I mean if Apple didn’t care about compatibility they would have never supported x86 translation layer in their arm64 version of macOS. They even expanded support to include AVX2 extensions and gave Linux VMs the ability to use this translation layer. Docker also works with x86 containers, something the X Elite can’t do yet.

but yeah they also drop support for 32bit apps which sucks. That’s why it’s good to have a MacBook as a backup. Windows will be king always due to the software backlog tho especially for gamers and engineering.

x86 to aarch64 was necessity for them that is why they included it in HW
Apple AMX
As you said dropped 32 bit support

 

[DavidC1]

Chadmont 32% 🤣

If that's not in Integer, rather in combined Int/FP, that's also a significant reduction from original expectations.

 

[Jan Olšan]

lol, that person is worse than Apple fanatics. I would wait for reviews before believing Intel marketing. I don’t care how “accurate” their slides are. It’s still marketing.

also I doubt the PL2 of the 285K is 177 watts. It will go higher.

Gaming power consumption usually isn't on PL2 level, it's not complete 100% load. Arrow Lake perhaps pushes it further down for light CPU load, while full all-core load still will be much doge, 100C go!

BTW, this probably explains the Bartlett Lake rumors. I did have hunch that it made no sense to make 12C/24T as "budget gaming option" as RGT initially tried to interpret it.
However, if Arrow Lake sucks for gaming, then it makes sense to make Bartlett Lake as "the gaming option" period, not a cheap product only.

I guess that is what it was all this time. Gotta say even as an AMD fan I expected Arrow Lake to be better at gaming, so I didn't buy in on this explanation back then

 

[Wolverine2349]

Gaming power consumption usually isn't on PL2 level, it's not complete 100% load. Arrow Lake perhaps pushes it further down for light CPU load, while full all-core load still will be much doge, 100C go!

BTW, this probably explains the Bartlett Lake rumors. I did have hunch that it made no sense to make 12C/24T as "budget gaming option" as RGT initially tried to interpret it.
However, if Arrow Lake sucks for gaming, then it makes sense to make Bartlett Lake as "the gaming option" period, not a cheap product only.

I guess that is what it was all this time. Gotta say even as an AMD fan I expected Arrow Lake to be better at gaming, so I didn't buy in on this explanation back then

Maybe it does. Maybe Arrow Lake will be great for gaming afterall. We will not know until its released.

Leaked slides often do not mean much. I remember vanilla Zen 5 leaked slides showed it beating 14900K but it was a huge disappointment. Maybe Intel sandbagging to ensure those Raptor Lake chips that are remaining on store shelves sell. I also remember Raptor Lake slides showing marginal at best performance increase over 5800X3D 2 years ago. And it turned out better than that. so maybe Intel sandbagging

And if Arrow Lake does indeed suck for gaming they better have the 12 P core and a stable one at that Bartlett Lake ready way sooner than Q3 2025 if it is indeed true.

And why would Intel release Arrow Lake that is worse for gaming than prior gen especially by a lot on DIY market? If the DIY market is really so niche couldn't they afford to ignore it rather than release something worse than predecessor. I mean DIY market is heavy gaming centric so would it make sense to release something to a more small market than just stay mobile only where bulk of sales are in the case the DIY target market has worse performance??

Maybe Bartlett Lake comes in LGA 1851 advanced platform features and LGA 1700 with the LGA 1700 platform limits on PCIe lanes???

 

[DavidC1]

And why would Intel release Arrow Lake that is worse for gaming than prior gen especially by a lot on DIY market?

Because they underperformed that's why. This is the best that both vendors can do and it wasn't enough. It's a strange question, like they've been holding back somehow.

 

[Josh128]

Looks like it's starting already.

https://twitter.com/x/status/1843673392534434076

https://twitter.com/x/status/1843606211112939711

This guy Jubileu is right up there with the most delusional fanatics out there. Intel winning= his very being.

 

[Saylick]

This guy Jubileu is right up there with the most delusional fanatics out there. Intel winning= his very being.

Him and that Prakhar guy on Xitter are the worst.

 

[CouncilorIrissa]

Him and that Prakhar guy on Xitter are the worst.

Hey, Prakhar is funny at least

 

[yuri69]

It looks bad, but still - it's worth waiting for memory-tuned reviews. You know games like Intel's memory setup.

 

[DavidC1]

@AMDK11 We told you Lion Cove is nothing special.

Lion Cove is 9% combined? I hope it's not. Cause we know Lion Cove adds more FP, meaning the gain in FP should be higher. One combination to get 9% is 6% Int and 15% FP....

32% combined for Skymont is 20% Int 55% FP assuming 65/35 split.

Both Zen 5c and Skymont seems pretty poor on C&C tests. The difference between MLC backed Skymont and Zen 5c is only about 11% per clock. Why is Zen 5c doing so bad? It barely outperforms Crestmont on Meteorlake.

 

[Saylick]

Hey, Prakhar is funny at least

I am never sure if he is or isn't paid by Intel to spent so much time marketing for them. Given his level of effort, I am at times convinced he must be hired by Intel as a promoter, and there's times where he clearly doesn't understand the info that he's sharing and then I'm not so sure he's getting paid, which would be sad since he spends such a big part of his waking hours being pro-Intel.

 

[cannedlake240]

If that's not in Integer, rather in combined Int/FP, that's also a significant reduction from original expectations.

It can't be integer lol that'd put it above LionCove

 

[igor_kavinski]

Given his level of effort, I am at times convinced he must be hired by Intel as a promoter, and there's times where he clearly doesn't understand the info that he's sharing and then I'm not so sure he's getting paid, which would be sad since he spends such a big part of his waking hours being pro-Intel.

You should feel sad for me too. AMD doesn't pay me either. A 9800X3D ES would've been nice, if not a 9184X

 

[DavidC1]

https://twitter.com/x/status/1843637230361030837

If the above is true, that would be the main contributing factor for less than expected performance not the moving to tiles.

My GUESS is that moving to tiles has killed their latency figures and this is hurting the performance.... but just a guess.

1.1GHz reduction is greater than the increase in ring clocks from Alder to Raptor. Alder's problem with the ring bus was that it had to clock down only when the E cores were active. If it's a universal 1.1GHz decrease, then it's very significant.

5GHz to 3.9GHz would result in 28% increase in L3 cache latency. 12900K had 4.1GHz peak ring clocks, so it's even slower than that.

 

[Josh128]

How everyone thought that Intels chip to chip interface would be so much faster than Zen 2/3/4/5's implementation is kind of puzzling. Chip to chip fanned-out copper traces were engineered for size and layout to transfer max frequency at acceptable inductive and capacitive reactances losses. Just because Intels tiles "look" neater and are physically a bit closer doesnt mean a whole lot from an electrical perspective. Wires / copper must be used for routing signals whether they are embedded in the silicon or not. ie they are there even though you cant see them. Until signals can be properly routed with light or ambient temp superconductors are discovered, we are not going to see any wild improvements any time soon.

 

[DavidC1]

How everyone thought that Intels chip to chip interface would be so much faster than Zen 2's implementation is kind of puzzling. Chip to chip fanned-out copper traces were engineered for size and layout to transfer max frequency at acceptable inductive and capacitive reactances losses. Just because Intels tiles "look" neater and are physically a bit closer doesnt mean a whole lot from an electrical perspective. Wires / copper must be used for routing signals whether they are embedded in the silicon or not. ie they are there even though you cant see them.

While it is possible that tile-to-tile is contributing indirectly to the slowness by requiring ring bus clocks to be degraded, we still have insufficient data to determine whether the tiles itself is the culprit.

We have two unreliable sources to base it on:
-Meteorlake, which is mobile only, and performance which vary from system to system.
-Arrowlake, which with the 1.1GHz reduction in ring clocks and thus L3 cache clocks will entirely explain the performance loss.

 

[adroc_thurston]

How everyone thought that Intels chip to chip interface would be so much faster than Zen 2's implementation is kind of puzzling

It is higher bandwidth and lower pJ/b than IFOP g3.
That's the point of advanced packaging.

-Arrowlake, which with the 1.1GHz reduction in ring clocks and thus L3 cache clocks will entirely explain the performance loss.

LNC has an additional meg of L2 to cope with poopoo L3 though.

 

[DavidC1]

It is higher bandwidth and lower pJ/b than IFOP g3.
That's the point of advanced packaging.

LNC has an additional meg of L2 to cope with poopoo L3 though.

Hence why the performance is more inconsistent, with some applications/games doing worse than others. You are still talking 3MB versus 30MB, or a 10x difference.

 

[Josh128]

It is higher bandwidth and lower pJ/b than IFOP g3.
That's the point of advanced packaging.

Higher bandwidth doesnt = lower latency though. And the power per bit figures come from Intel, correct? Do these companies not lie all the time or at least warp the hell out of the truth in publicly released info?

 

[adroc_thurston]

You are still talking 3MB versus 30MB, or a 10x difference.

Games aren't purely 1T, it's more like 24M versus 36M or therein.

Higher bandwidth doesnt = lower latency though.

Well yeah, latency is a factor of your fabric and uncore.

 

[DavidC1]

Games aren't purely 1T, it's more like 24M versus 36M or therein.

You are talking about single digit % differences in performance here for the most part. Having a part of that hierarchy increase latency by 28% can explain those differences.

 

[adroc_thurston]

You are talking about single digit % differences in performance here for the most part. Having a part of that hierarchy increase latency by 28% can explain those differences.

Yeah but you also have more raw capacity at 17clk a core, plus L1.5d on top of that. LNC by all accounts should cope very well with slower L3.
Like this isn't the first time Intel L3 got slower. They coped well before that, so unlikely LNC copes any worse than SNC in TGL did.

 

[AMDK11]

@AMDK11 We told you Lion Cove is nothing special.

Lion Cove is 9% combined? I hope it's not. Cause we know Lion Cove adds more FP, meaning the gain in FP should be higher. One combination to get 9% is 6% Int and 15% FP....

32% combined for Skymont is 20% Int 55% FP assuming 65/35 split.

Both Zen 5c and Skymont seems pretty poor on C&C tests. The difference between MLC backed Skymont and Zen 5c is only about 11% per clock. Why is Zen 5c doing so bad? It barely outperforms Crestmont on Meteorlake.

Of course, ArrowLake is special in terms of core microarchitecture. It is not special in terms of IPC LionCove.

I wrote about core microarchitecture, not IPC. But I must admit that the average 9% higher IPC compared to RaptorCove is a big disappointment for me. I was counting on about 15-20%.

 

[adroc_thurston]

Why is Zen 5c doing so bad?

Low clocks, low cache. It's an overbloated LP ghetto.
The one in KRK should do a bit better given it's a uni-ccx with 16M L3$.

 

[poke01]

This gloom will only last till Nova lake.

on paper NVL should be greatest change since Alder Lake, APX, 14A and total new architectures to boot. save money and wait till then if your on Alder lake or Zen4/5.

Nova lake should better than Zen6 too as it will have APX and AVX10. But as always things go sideways at Intel so who the ***** knows