Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DavidC1]

Otherwise they would say that the PBU is completely new with new algorithms or something like that and not that the PBU block is 8 times larger.

Sure it is! It's logical analysis. Enlarging the entire BPU block by 8x is prohibitive, just based on your pictures you had a while ago.

And it's not supported by performance, which means either A) the increase is nowhere near you are expecting. B) The team, not just the design needs to be replaced with such unbalanced design choices.

Like I said, enlarging entire BPU would mean ridiculous sizes such as a 60K BTB, which is unprecedented in the history of CPUs, and we aren't in the golden days of scaling anymore where they can afford such braindead decisions. We've been talking about them bloating ROB sizes, but now you are saying they'll do even worse but with the branch predictor?

They would have said "8x Branch prediction capability/BTB sizes". Instead they said prediction block. It means it's a subset. Do you expect that it'll suddenly go from 14% to say 30% or something? It's Zen 5 level hopium. What would justify them increasing one significant block that much? If instead they moved to 8x decoder width or ROB size, would you still think it's a sane decision? Even if they did go to 48-wide decoder or 4,000 entry ROB the best they would have got from that waste is 5-10% at most.

 

[DrMrLordX]

TSMC's N3B capacity is limited, N3E is where the volume is. For either issue the solution would have been for Intel to port to N3E, but for whatever reason they chose not to. So if that means RPL has to continue on longer as a result that's kind of their fault, since I doubt TSMC was forcing them to choose/stick with N3B.

Intel has as much N3B as $10 billion would buy them. If they're wafer-limited for Arrow Lake, it's because Intel couldn't afford to buy more (and/or TSMC put limits on how many fabs they could convert to fill Intel's order; they had to convert a research fab to full production, allegedly).

 

[DavidC1]

Lol, Bionic Squash says only cache changes for Arrowlake's Lion Cove.

It won't be anything worth noting folks. I keep telling everyone, in the world of semis, you have to be prepared to be disappointed. 1-2% gains do NOT come easy.

 

[dttprofessor]

Intel has as much N3B as $10 billion would buy them. If they're wafer-limited for Arrow Lake, it's because Intel couldn't afford to buy more (and/or TSMC put limits on how many fabs they could convert to fill Intel's order; they had to convert a research fab to full production, allegedly).

Intel foreveo volume is limited till late 2025.5m per month about.

 

[DrMrLordX]

Intel foreveo volume is limited till late 2025.5m per month about.

So it's a packaging plant issue? Hmm interesting.

 

[DavidC1]

According to AMD, the 16% gains for Zen 5 is split between:
-Data Bandwidth
-Execution/Retire
-Decode/Opcache
-Fetch/Branch Prediction

Eyeballing it in order I would say, 5%, 5%, 4%, 2%.

This is the reality folks. Each gains are responsible for mere few % gains. In a general purpose CPU, the gains come from a balanced increase of ALL parts of the CPU.

 

[SiliconFly]

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[dttprofessor]

I don't think thats accurate. They now have 2 fabs for foveros. The new one is ramping up already. Foveros isn't a bottleneck anymore.

The biggest one is on Malaysia，building now.

 

[cebri1]

https://twitter.com/x/status/1812852062444482740

 

[coercitiv]

https://twitter.com/x/status/1812852062444482740

Intel's Bartlett Lake-S is incoming, but not to desktop PCs — chips will debut for Intel's NEX group

Intel preps socketed Bartlett Lake-S for network and edge systems.

www.tomshardware.com

The real news it the leaker says they will be sold for consumers on LGA 1700 (including the 10 and 12P variants)

 

[SiliconFly]

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[Saylick]

2 passive dies for PTL. Looks like Intel is converging on a typical configuration for their tiled architectures now, where one die is for CPU compute, another die is for the GPU, and the last die is basically IO and everything else. Oh, and a base tile.

https://twitter.com/x/status/1812898063502938260

 

[DavidC1]

2 passive dies for PTL. Looks like Intel is converging on a typical configuration for their tiled architectures now, where one die is for CPU compute, another die is for the GPU, and the last die is basically IO and everything else. Oh, and a base tile.

Lol, not expecting too much from the LP E cores again.

 

[SiliconFly]

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[DavidC1]

Lunar Lake has 4 Skymont LPE cores. And it seems to be pretty much perfect.

Because Lunarlake actually has a sane implementation of having only two clusters, and the E core has high dynamic range to address all the way from nearly idle workloads to quite high ones, and unlike MTL it doesn't need to skip to another tile to have it on.

Meteorlake is a complete and utter fail for example. 150mW savings in the Intel demo scenario, so that's like fly on an elephant's butt, and other times it doesn't work. So with Pantherlake they want to adopt MTL's approach again?

 

[mikk]

Because Lunarlake actually has a sane implementation of having only two clusters, and the E core has high dynamic range to address all the way from nearly idle workloads to quite high ones, and unlike MTL it doesn't need to skip to another tile to have it on.

Meteorlake is a complete and utter fail for example. 150mW savings in the Intel demo scenario, so that's like fly on an elephant's butt, and other times it doesn't work. So with Pantherlake they want to adopt MTL's approach again?

Who says they will adopt the same MTL style? Intel clearly didn't. It doesn't even use the same amount of tiles. You think they will adopt it which is probably just nonsense.

 

[SiliconFly]

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[mikk]

True. PTL tile setup is surely gonna be very different from MTL. I don't think Intel's design team is stupid enough to repeat the same mistake again after two years.

LPE cores and IMC also goes into the compute tile, that alone will make a big difference. So for light load they can still disable the Ringbus like on LNL for a much improved battery life. Same MTL style lol.

 

[dullard]

Because Lunarlake actually has a sane implementation of having only two clusters, and the E core has high dynamic range to address all the way from nearly idle workloads to quite high ones, and unlike MTL it doesn't need to skip to another tile to have it on.

Meteorlake is a complete and utter fail for example. 150mW savings in the Intel demo scenario, so that's like fly on an elephant's butt, and other times it doesn't work. So with Pantherlake they want to adopt MTL's approach again?

Let me get this straight. Is it your theory is that:
1) Meteor Lake's implementation is bad,
2) Intel fixed it with Lunar Lake,
Therefore,
3) Intel will break it again and go back to the old implementation for Panther Lake?

If I understand you correctly, what do you base #3 on? They already combined the SOC and Compute tiles to eliminate the complaint you have about skipping to other tiles.

 

[DavidC1]

If I understand you correctly, what do you base #3 on? They already combined the SOC and Compute tiles to eliminate the complaint you have about skipping to other tiles.

If they have it on one die, it's better.

But we should question why the successor of a product that is very low power is suddenly going back to a setup similar to the predecessor - one that did not work very well. By having the third cluster you add additional complexities that they have to make up such as dealing with switching latencies and scheduler complexity.

 

[dullard]

If they have it on one die, it's better.

But we should question why the successor of a product that is very low power is suddenly going back to a setup similar to the predecessor - one that did not work very well. By having the third cluster you add additional complexities that they have to make up such as dealing with switching latencies and scheduler complexity.

They already reduced complexity by getting rid of the 4th thread type (the hyperthread). They reduced the performance gaps between cores, meaning less reason to switch cores. Plus by then, more and more software will be programmed to prefer or to avoid specific types of cores.

 

[Bouowmx]

2 passive dies for PTL. Looks like Intel is converging on a typical configuration for their tiled architectures now, where one die is for CPU compute, another die is for the GPU, and the last die is basically IO and everything else. Oh, and a base tile.

To confirm my understanding:
Given the similarity of the platform controller to Lunar Lake's, the compute tile has the LP E cores (software can directly use them?) and memory controller, not like in Meteor Lake. But, Arrow Lake still has the old style.

 

[511]

If they have it on one die, it's better.

But we should question why the successor of a product that is very low power is suddenly going back to a setup similar to the predecessor - one that did not work very well. By having the third cluster you add additional complexities that they have to make up such as dealing with switching latencies and scheduler complexity.

This is for one reason going back to inhouse manufacturing also they don't want to fab for bigger GPUs on Intel Node for now so N3E for that IO is just cheap silicon also i guess they will just add 8E to the LNL Design and make other enhancement while keeping off ring LPE seperate in the same compute tile it will not be worse than MTL

 

[Gideon]

LPE cores and IMC also goes into the compute tile, that alone will make a big difference. So for light load they can still disable the Ringbus like on LNL for a much improved battery life. Same MTL style lol.

Interesting, where is this info from?

 

[Goop_reformed]

W1zzard from TPU said Arrowlake will be faster than both zen 5 and Zen 4x3d:

AMD Zen 5 Technical Deep Dive

AMD has finally shared technical details for their next-gen Zen 5 microarchitecture, which will power the new Ryzen 9000 desktop processors and the Ryzen AI 300 Series laptop CPUs. We detail all the technical innovations, including overclocking, and how AMD achieved +16% IPC.

www.techpowerup.com